本文主要是介绍An Independent Analysis Altera’s FPGA Floating-point DSP Design Flow，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
原文链接：http://www.altera.com.cn/literature/wp/wp-01166-bdti-altera-floating-point-dsp.pdf
后续按照文章测试方法，做一个Xilinx DSP架构FPGA对比测试，就更有意义了。
不过记住：人脑是最好的优化器！
简介如下：
OVERVIEW
FPGAs are increasingly used as parallel processing engines for demanding digital
signal processing applications. Benchmark results show that on highly parallelizable
workloads, FPGAs can achieve higher performance and superior cost/performance
compared to digital signal processors (DSPs) and general-purpose CPUs. However, to
date, FPGAs have been used almost exclusively for fixed-point DSP designs. FPGAs
have not been viewed as an effective platform for applications requiring high-performance
floating-point computations. FPGA floating-point efficiency and performance has been
limited due to long processing latencies and routing congestion. In addition, the traditional
FPGA design flow, based on writing register-transfer-level hardware descriptions in
Verilog or VHDL, is not well suited to implementing complex floating-point algorithms.
Altera has developed a new floating-point design flow intended to streamline the
process of implementing floating-point digital signal processing algorithms on Altera
FPGAs, and to enable those designs to achieve higher performance and efficiency than
previously possible. Rather than building a datapath consisting of elementary floatingpoint operators (for example, multiplication followed by addition followed by squaring), the
floating-point compiler generates a fused datapath that combines elementary operators
into a single function or datapath. In doing so, it eliminates the redundancies present in
traditional floating-point FPGA designs. In addition, the Altera design flow is a high-level
model-based flow using Altera’s DSP Builder Advanced Blockset and the MathWorks’
MATLAB and Simulink tools. Altera hopes that by working at a high level, FPGA
designers will be able to implement and verify complex floating-point algorithms more
quickly than would be possible with traditional HDL-based design.
BDTI performed an independent analysis of Altera’s floating-point DSP design
flow. BDTI’s objective was to assess the performance that can be obtained on Altera
FPGAs for demanding floating-point DSP applications, and to evaluate the ease-of-use of
Altera’s floating-point DSP design flow. This paper presents BDTI’s findings, along with
background and methodology details.
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