本文主要是介绍HDLbits:Fsm onehot，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
这道题理解有误，以为s0=10'b0000000001，s0=10'b0000000010，写成了如下的代码（有误）：
module top_module(input in,input [9:0] state,output [9:0] next_state,output out1,output out2);parameter s0=10'b0000000001,s1=10'b0000000010,s2=10'b0000000100,s3=10'b0000001000,s4=10'b0000010000,s5=10'b0000100000,s6=10'b0001000000,s7=10'b0010000000,s8=10'b0100000000,s9=10'b1000000000,s_defualt=10'b0000000000;always@(*)begincase(state)s0: next_state = in?s1:s0;s1: next_state = in?s2:s0;s2: next_state = in?s3:s0;s3: next_state = in?s4:s0; s4: next_state = in?s5:s0;s5: next_state = in?s6:s8;s6: next_state = in?s7:s9;s7: next_state = in?s7:s0;s8: next_state = in?s1:s0;s9: next_state = in?s1:s0;default:next_state = s_defualt;endcaseendassign out1 = (state == s8 ||state == s9); assign out2 = (state == s7 ||state == s9); endmodule后来发现其实是state[0]表示s0，state[1]表示s1，但并没说其他位一定为0，正确答案如下：
module top_module(input in,input [9:0] state,output [9:0] next_state,output out1,output out2);assign next_state[0] = (state[1] | state[2] | state[3] | state[4] | state[7]| state[8]| state[9]| state[0])& ~in;assign next_state[1] = (state[8] | state[9] | state[0]) & in; assign next_state[2] = state[1] & in; assign next_state[3] = state[2] & in; assign next_state[4] = state[3] & in; assign next_state[5] = state[4] & in; assign next_state[6] = state[5] & in; assign next_state[7] = (state[7] | state[6]) & in; assign next_state[8] = state[5] & ~in; assign next_state[9] = state[6] & ~in;assign out1 =(state[8]==1 || state[9]==1);assign out2 =(state[7]==1 || state[9]==1);
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