本文主要是介绍创建 AD9361 的 vivado 工程,纯FPGA配置，不使用ARM程序，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
前言
AD9361 的配置程序，如果使用官方的，就必须用ps进行配置，复杂不好使，如果直接使用FPGA配置，将会特别的简单。
配置软件
创建一份完整的寄存器配置表
//************************************************************
// AD9361 R2 Auto Generated Initialization Script: This script was
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: LTE 10 MHz
// REFCLK_IN: 38.400 MHzRESET_FPGA
RESET_DUT BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
ReadPartNumber
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 38.400000,1,2 // Sets local variables in script engine, user can ignore
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,17 // Enable Clocks
WAIT 20 // waits 20 ms//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1
SPIWrite 046,04 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,00 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,20 // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,13 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,19 // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 360.000 us (Done when 0x05E[7]==1)SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked)SPIWrite 002,DE // Setup Tx Digital Filters/ Channels
SPIWrite 003,DE // Setup Rx Digital Filters/ Channels
SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
SPIWrite 00A,02 // Set BBPLL post divide rate//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
SPIWrite 010,C8 // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
SPIWrite 011,00 // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
SPIWrite 012,02 // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
SPIWrite 006,0F // PPORT Rx Delay (adjusts Tco Dataclk->Data)
SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data)//************************************************************
// Setup AuxDAC
//************************************************************
SPIWrite 018,00 // AuxDAC1 Word[9:2]
SPIWrite 019,00 // AuxDAC2 Word[9:2]
SPIWrite 01A,00 // AuxDAC1 Config and Word[1:0]
SPIWrite 01B,00 // AuxDAC2 Config and Word[1:0]
SPIWrite 023,FF // AuxDAC Manaul/Auto Control
SPIWrite 026,00 // AuxDAC Manual Select Bit/GPO Manual Select
SPIWrite 030,00 // AuxDAC1 Rx Delay
SPIWrite 031,00 // AuxDAC1 Tx Delay
SPIWrite 032,00 // AuxDAC2 Rx Delay
SPIWrite 033,00 // AuxDAC2 Tx Delay//************************************************************
// Setup AuxADC
//************************************************************
SPIWrite 00B,00 // Temp Sensor Setup (Offset)
SPIWrite 00C,00 // Temp Sensor Setup (Temp Window)
SPIWrite 00D,03 // Temp Sensor Setup (Periodic Measure)
SPIWrite 00F,04 // Temp Sensor Setup (Decimation)
SPIWrite 01C,10 // AuxADC Setup (Clock Div)
SPIWrite 01D,01 // AuxADC Setup (Decimation/Enable)//************************************************************
// Setup Control Outs
//************************************************************
SPIWrite 035,00 // Ctrl Out index
SPIWrite 036,FF // Ctrl Out [7:0] output enable//************************************************************
// Setup GPO
//************************************************************
SPIWrite 03A,25 // Set number of REFCLK cycles for 1us delay timer
SPIWrite 020,00 // GPO Auto Enable Setup in RX and TX
SPIWrite 027,03 // GPO Manual and GPO auto value in ALERT
SPIWrite 028,00 // GPO_0 RX Delay
SPIWrite 029,00 // GPO_1 RX Delay
SPIWrite 02A,00 // GPO_2 RX Delay
SPIWrite 02B,00 // GPO_3 RX Delay
SPIWrite 02C,00 // GPO_0 TX Delay
SPIWrite 02D,00 // GPO_1 TX Delay
SPIWrite 02E,00 // GPO_2 TX Delay
SPIWrite 02F,00 // GPO_3 TX Delay//************************************************************
// Setup RF PLL non-frequency-dependent registers
//************************************************************
SPIWrite 261,00 // Set Rx LO Power mode
SPIWrite 2A1,00 // Set Tx LO Power mode
SPIWrite 248,0B // Enable Rx VCO LDO
SPIWrite 288,0B // Enable Tx VCO LDO
SPIWrite 246,02 // Set VCO Power down TCF bits
SPIWrite 286,02 // Set VCO Power down TCF bits
SPIWrite 249,8E // Set VCO cal length
SPIWrite 289,8E // Set VCO cal length
SPIWrite 23B,80 // Enable Rx VCO cal
SPIWrite 27B,80 // Enable Tx VCO cal
SPIWrite 243,0D // Set Rx prescaler bias
SPIWrite 283,0D // Set Tx prescaler bias
SPIWrite 23D,00 // Clear Half VCO cal clock setting
SPIWrite 27D,00 // Clear Half VCO cal clock settingSPIWrite 015,0C // Set Dual Synth mode bit
SPIWrite 014,15 // Set Force ALERT State bit
SPIWrite 013,01 // Set ENSM FDD mode
WAIT 1 // waits 1 msSPIWrite 23D,04 // Start RX CP cal
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 480.000 (us)(Done when 0x244[7]==1)SPIWrite 27D,04 // Start TX CP cal
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 480.000 (us)(Done when 0x284[7]==1)SPIWrite 23D,00 // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT
SPIWrite 27D,00 // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT
//************************************************************
// FDD RX,TX Synth Frequency: 2400.000000,2500.000000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 23A,4A // Set VCO Output level[3:0]
SPIWrite 239,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 242,0D // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 238,68 // Set VCO Cal Offset[3:0]
SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 251,09 // Set VCO Varactor Reference[3:0]
SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
SPIWrite 23B,91 // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 23E,D4 // Set Synth Loop Filter C2 and C1
SPIWrite 23F,DF // Set Synth Loop Filter R1 and C3
SPIWrite 240,09 // Set Synth Loop Filter R3//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 27A,4A // Set VCO Output level[3:0]
SPIWrite 279,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 282,0D // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 278,70 // Set VCO Cal Offset[3:0]
SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 291,09 // Set VCO Varactor Reference[3:0]
SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
SPIWrite 27B,8F // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 27E,D4 // Set Synth Loop Filter C2 and C1
SPIWrite 27F,DF // Set Synth Loop Filter R1 and C3
SPIWrite 280,09 // Set Synth Loop Filter R3//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0]
SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8]
SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16]
SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8]
SPIWrite 231,7D // Write Rx Synth Integer Freq Word[7:0]
SPIWrite 005,11 // Set LO divider setting
SPIWrite 273,A8 // Write Tx Synth Fractional Freq Word[7:0]
SPIWrite 274,AA // Write Tx Synth Fractional Freq Word[15:8]
SPIWrite 275,1A // Write Tx Synth Fractional Freq Word[22:16]
SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8]
SPIWrite 271,82 // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
SPIWrite 005,11 // Set LO divider setting
SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked)
SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked)//************************************************************
// Program Mixer GM Sub-table
//************************************************************
SPIWrite 13F,02 // Start Clock
SPIWrite 138,0F // Addr Table Index
SPIWrite 139,78 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,00 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,0E // Addr Table Index
SPIWrite 139,74 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,0D // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,0D // Addr Table Index
SPIWrite 139,70 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,15 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,0C // Addr Table Index
SPIWrite 139,6C // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,1B // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,0B // Addr Table Index
SPIWrite 139,68 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,21 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,0A // Addr Table Index
SPIWrite 139,64 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,25 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,09 // Addr Table Index
SPIWrite 139,60 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,29 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,08 // Addr Table Index
SPIWrite 139,5C // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,2C // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,07 // Addr Table Index
SPIWrite 139,58 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,2F // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,06 // Addr Table Index
SPIWrite 139,54 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,31 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,05 // Addr Table Index
SPIWrite 139,50 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,33 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,04 // Addr Table Index
SPIWrite 139,4C // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,34 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,03 // Addr Table Index
SPIWrite 139,48 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,35 // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,02 // Addr Table Index
SPIWrite 139,30 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,3A // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,01 // Addr Table Index
SPIWrite 139,18 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,3D // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 138,00 // Addr Table Index
SPIWrite 139,00 // Gain
SPIWrite 13A,00 // Bias
SPIWrite 13B,3E // GM
SPIWrite 13F,06 // Write Words
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 13F,02 // Clear Write Bit
SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write)
SPIWrite 13C,00 // Delay ~1us (Dummy Write)
SPIWrite 13F,00 // Stop Clock//************************************************************
// Program Rx Gain Tables with GainTable2300MHz.csv
//************************************************************SPIWrite 137,1A // Start Gain Table Clock
SPIWrite 130,00 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,01 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,02 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,03 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,01 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,04 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,02 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,05 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,03 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,06 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,04 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,07 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,05 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,08 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,03 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,09 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,04 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0A // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,05 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0B // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,06 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0C // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,07 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0D // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,08 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0E // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,09 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,0F // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0A // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,10 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0B // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,11 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0C // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,12 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0D // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,13 // Gain Table Index
SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0E // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,14 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,09 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,15 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0A // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,16 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0B // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,17 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0C // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,18 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0D // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,19 // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0E // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1A // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,0F // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1B // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,10 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1C // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2B // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1D // Gain Table Index
SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2C // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1E // Gain Table Index
SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,27 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,1F // Gain Table Index
SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,28 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,20 // Gain Table Index
SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,29 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,21 // Gain Table Index
SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2A // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,22 // Gain Table Index
SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2B // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,23 // Gain Table Index
SPIWrite 131,24 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,21 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,24 // Gain Table Index
SPIWrite 131,24 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,22 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,25 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,20 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,26 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,21 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,27 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,22 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,28 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,23 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,29 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,24 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2A // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,25 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2B // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,26 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2C // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,27 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2D // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,28 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2E // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,29 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,2F // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2A // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,30 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2B // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,31 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2C // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,32 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2D // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,33 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2E // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,34 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2F // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,35 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,30 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,36 // Gain Table Index
SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,31 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,37 // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2E // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,38 // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,2F // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,39 // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,30 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3A // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,31 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3B // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,32 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3C // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,33 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3D // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,34 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3E // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,35 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,3F // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,36 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,40 // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,37 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,41 // Gain Table Index
SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,42 // Gain Table Index
SPIWrite 131,65 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,43 // Gain Table Index
SPIWrite 131,66 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,44 // Gain Table Index
SPIWrite 131,67 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,45 // Gain Table Index
SPIWrite 131,68 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,46 // Gain Table Index
SPIWrite 131,69 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,47 // Gain Table Index
SPIWrite 131,6A // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,48 // Gain Table Index
SPIWrite 131,6B // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,49 // Gain Table Index
SPIWrite 131,6C // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4A // Gain Table Index
SPIWrite 131,6D // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4B // Gain Table Index
SPIWrite 131,6E // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4C // Gain Table Index
SPIWrite 131,6F // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,38 // TIA & LPF Word
SPIWrite 133,20 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4D // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4E // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,4F // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,50 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,51 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,52 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,53 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,54 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,55 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,56 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,57 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,58 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,59 // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 130,5A // Gain Table Index
SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word
SPIWrite 132,00 // TIA & LPF Word
SPIWrite 133,00 // DC Cal bit & Dig Gain Word
SPIWrite 137,1E // Write Words
SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 137,1A // Clear Write Bit
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 134,00 // Dummy Write to delay ~1us
SPIWrite 137,00 // Stop Gain Table Clock
//************************************************************
// Setup Rx Manual Gain Registers
//************************************************************
SPIWrite 0FA,E0 // Gain Control Mode Select
SPIWrite 0FB,08 // Table, Digital Gain, Man Gain Ctrl
SPIWrite 0FC,23 // Incr Step Size, ADC Overrange Size
SPIWrite 0FD,4C // Max Full/LMT Gain Table Index
SPIWrite 0FE,44 // Decr Step Size, Peak Overload Time
SPIWrite 100,6F // Max Digital Gain
SPIWrite 104,2F // ADC Small Overload Threshold
SPIWrite 105,3A // ADC Large Overload Threshold
SPIWrite 107,2B // Small LMT Overload Threshold
SPIWrite 108,31 // Large LMT Overload Threshold
SPIWrite 109,4C // Rx1 Full/LMT Gain Index
SPIWrite 10A,F8 // Rx1 LPF Gain Index
SPIWrite 10B,00 // Rx1 Digital Gain Index
SPIWrite 10C,4C // Rx2 Full/LMT Gain Index
SPIWrite 10D,18 // Rx2 LPF Gain Index
SPIWrite 10E,00 // Rx2 Digital Gain Index
SPIWrite 114,30 // Low Power Threshold
SPIWrite 11A,1C // Initial LMT Gain Limit
SPIWrite 081,00 // Tx Symbol Gain Control
//************************************************************
// RX Baseband Filter Tuning (Real BW: 4.500000 MHz) 3dB Filter
// Corner @ 6.300000 MHz)
//************************************************************
SPIWrite 1FB,04 // RX Freq Corner (MHz)
SPIWrite 1FC,40 // RX Freq Corner (Khz)
SPIWrite 1F8,12 // Rx BBF Tune Divider[7:0]
SPIWrite 1F9,1E // RX BBF Tune Divider[8]SPIWrite 1D5,3F // Set Rx Mix LO CM
SPIWrite 1C0,03 // Set GM common mode
SPIWrite 1E2,02 // Enable Rx1 Filter Tuner
SPIWrite 1E3,02 // Enable Rx2 Filter Tuner
SPIWrite 016,80 // Start RX Filter Tune
WAIT_CALDONE RXFILTER,2000 // Wait for RX filter to tune, Max Cal Time: 11.169 us (Done when 0x016[7]==0)SPIWrite 1E2,03 // Disable Rx Filter Tuner (Rx1)
SPIWrite 1E3,03 // Disable Rx Filter Tuner (Rx2)
//************************************************************
// TX Baseband Filter Tuning (Real BW: 4.500000 MHz) 3dB Filter
// Corner @ 7.200000 MHz)
//************************************************************
SPIWrite 0D6,10 // TX BBF Tune Divider[7:0]
SPIWrite 0D7,1E // TX BBF Tune Divider[8]SPIWrite 0CA,22 // Enable Tx Filter Tuner
SPIWrite 016,40 // Start Tx Filter Tune
WAIT_CALDONE TXFILTER,2000 // Wait for TX filter to tune, Max Cal Time: 5.778 us (Done when 0x016[6]==0)SPIWrite 0CA,26 // Disable Tx Filter Tuner (Both Channels)
//************************************************************
// RX TIA Setup: Setup values scale based on RxBBF calibration
// results. See information in Calibration Guide.
//************************************************************
SPIRead 1EB // Read RXBBF C3(MSB)
SPIRead 1EC // Read RXBBF C3(LSB)
SPIRead 1E6 // Read RXBBF R2346
SPIWrite 1DB,60 // Set TIA selcc[2:0]
SPIWrite 1DD,0A // Set RX TIA1 C MSB[6:0]
SPIWrite 1DF,0A // Set RX TIA2 C MSB[6:0]
SPIWrite 1DC,40 // Set RX TIA1 C LSB[5:0]
SPIWrite 1DE,40 // Set RX TIA2 C LSB[5:0]//************************************************************
// TX Secondary Filter Calibration Setup: Real Bandwidth
// 4.500000MHz, 3dB Corner @ 22.500000MHz
//************************************************************
SPIWrite 0D2,3B // TX Secondary Filter PDF Cap cal[5:0]
SPIWrite 0D1,0C // TX Secondary Filter PDF Res cal[3:0]
SPIWrite 0D0,59 // Pdampbias //************************************************************
// ADC Setup: Tune ADC Performance based on RX analog filter tune
// corner. Real Bandwidth: 4.303445 MHz, ADC Clock Frequency:
// 245.760000 MHz. The values in registers 0x200 - 0x227 need to be
// calculated using the equations in the Calibration Guide.
//************************************************************
SPIRead 1EB // Read RxBBF C3 MSB after calibration
SPIRead 1EC // Read RxBBF C3 LSB after calibration
SPIRead 1E6 // Read RxBBF R3 after calibrationSPIWrite 200,00
SPIWrite 201,00
SPIWrite 202,00
SPIWrite 203,24
SPIWrite 204,24
SPIWrite 205,00
SPIWrite 206,00
SPIWrite 207,7C
SPIWrite 208,53
SPIWrite 209,3C
SPIWrite 20A,4B
SPIWrite 20B,34
SPIWrite 20C,4E
SPIWrite 20D,32
SPIWrite 20E,00
SPIWrite 20F,7F
SPIWrite 210,7F
SPIWrite 211,7F
SPIWrite 212,49
SPIWrite 213,49
SPIWrite 214,49
SPIWrite 215,4C
SPIWrite 216,4C
SPIWrite 217,4C
SPIWrite 218,2E
SPIWrite 219,98
SPIWrite 21A,1B
SPIWrite 21B,13
SPIWrite 21C,98
SPIWrite 21D,1B
SPIWrite 21E,13
SPIWrite 21F,98
SPIWrite 220,1B
SPIWrite 221,27
SPIWrite 222,27
SPIWrite 223,40
SPIWrite 224,40
SPIWrite 225,2C
SPIWrite 226,00
SPIWrite 227,00
//************************************************************
// Setup and Run BB DC and RF DC Offset Calibrations
//************************************************************
SPIWrite 193,3F
SPIWrite 190,0F // Set BBDC tracking shift M value, only applies when BB DC tracking enabled
SPIWrite 194,01 // BBDC Cal setting
SPIWrite 016,01 // Start BBDC offset cal
WAIT_CALDONE BBDC,2000 // BBDC Max Cal Time: 13151.042 us. Cal done when 0x016[0]==0SPIWrite 185,20 // Set RF DC offset Wait Count
SPIWrite 186,32 // Set RF DC Offset Count[7:0]
SPIWrite 187,24 // Settings for RF DC cal
SPIWrite 18B,83 // Settings for RF DC cal
SPIWrite 188,05 // Settings for RF DC cal
SPIWrite 189,30 // Settings for RF DC cal
SPIWrite 016,02 // Start RFDC offset cal
WAIT_CALDONE RFDC,2000 // RFDC Max Cal Time: 178923.828 us//************************************************************
// Tx Quadrature Calibration Settings
//************************************************************
SPIRead 0A3 // Masked Read: Read lower 6 bits, overwrite [7:6] below
SPIWrite 0A0,15 // Set TxQuadcal NCO frequency
SPIWrite 0A3,00 // Set TxQuadcal NCO frequency (Only update bits [7:6])
SPIWrite 0A1,7B // Tx Quad Cal Configuration, Phase and Gain Cal Enable
SPIWrite 0A9,FF // Set Tx Quad Cal Count
SPIWrite 0A2,7F // Set Tx Quad Cal Kexp
SPIWrite 0A5,01 // Set Tx Quad Cal Magnitude Threshhold
SPIWrite 0A6,01 // Set Tx Quad Cal Magnitude Threshhold
SPIWrite 0AA,25 // Set Tx Quad Cal Gain Table index
SPIWrite 0A4,F0 // Set Tx Quad Cal Settle Count
SPIWrite 0AE,00 // Set Tx Quad Cal LPF Gain index incase Split table mode usedSPIWrite 169,C0 // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
SPIWrite 016,10 // Start Tx Quad cal
WAIT_CALDONE TXQUAD,2000 // Wait for cal to complete (Done when 0x016[4]==0)SPIWrite 16A,75 // Set Kexp Phase
SPIWrite 16B,95 // Set Kexp Amplitude & Prevent Positive Gain Bit
SPIWrite 169,CF // Enable Rx Quadrature Calibration Tracking
SPIWrite 18B,AD // Enable BB and RF DC Tracking Calibrations
SPIWrite 012,02 // Cals done, Set PPORT Config
SPIWrite 013,01 // Set ENSM FDD/TDD bit
SPIWrite 015,0C // Set Dual Synth Mode, FDD External Control bits properly//************************************************************
// Set Tx Attenuation: Tx1: 10.00 dB, Tx2: 10.00 dB
//************************************************************
SPIWrite 073,28
SPIWrite 074,00
SPIWrite 075,28
SPIWrite 076,00
//************************************************************
// Setup RSSI and Power Measurement Duration Registers
//************************************************************
SPIWrite 150,0E // RSSI Measurement Duration 0, 1
SPIWrite 151,00 // RSSI Measurement Duration 2, 3
SPIWrite 152,FF // RSSI Weighted Multiplier 0
SPIWrite 153,00 // RSSI Weighted Multiplier 1
SPIWrite 154,00 // RSSI Weighted Multiplier 2
SPIWrite 155,00 // RSSI Weighted Multiplier 3
SPIWrite 156,00 // RSSI Delay
SPIWrite 157,00 // RSSI Wait
SPIWrite 158,0D // RSSI Mode Select
SPIWrite 15C,67 // Power Measurement Duration转化为 FPGA代码
//************************************************************
// AD9361 R2 Auto Generated Initialization Script: This script was
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: LTE 10 MHz
// REFCLK_IN: 38.400 MHz
function [18:0] cmd_data;
input [11:0] index;begincase(index)12'd0 :cmd_data={1'b1,10'h000,8'h00};12'd1 :cmd_data={1'b1,10'h3df,8'h01};// Required for proper operation12'd2 :cmd_data={1'b1,10'h2a6,8'h0e};// Enable Master Bias12'd3 :cmd_data={1'b1,10'h2a8,8'h0e};// Set Bandgap Trim12'd4 :cmd_data={1'b1,10'h292,8'h10};12'd5 :cmd_data={1'b1,10'h293,8'h00};12'd6 :cmd_data={1'b1,10'h294,8'h00};12'd7 :cmd_data={1'b1,10'h2ab,8'h07};// Set RF PLL reflclk scale to REFCLK * 212'd8 :cmd_data={1'b1,10'h2ac,8'hff};// Set RF PLL reflclk scale to REFCLK * 212'd9 :cmd_data={1'b1,10'h009,8'h17};// Enable Clocks
//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************12'd10 :cmd_data={1'b1,10'h045,8'h00};// Set BBPLL reflclk scale to REFCLK /112'd11 :cmd_data={1'b1,10'h046,8'h04};// Set BBPLL Loop Filter Charge Pump current12'd12 :cmd_data={1'b1,10'h048,8'he8};// Set BBPLL Loop Filter C1, R112'd13 :cmd_data={1'b1,10'h049,8'h5b};// Set BBPLL Loop Filter R2, C2, C112'd14 :cmd_data={1'b1,10'h04a,8'h35};// Set BBPLL Loop Filter C3,R212'd15 :cmd_data={1'b1,10'h04b,8'he0};// Allow calibration to occur and set cal count to 1024 for max accuracy12'd16 :cmd_data={1'b1,10'h04e,8'h10};// Set calibration clock to REFCLK/4 for more accuracy12'd17 :cmd_data={1'b1,10'h043,8'h00};// BBPLL Freq Word (Fractional[7:0])12'd18 :cmd_data={1'b1,10'h042,8'h20};// BBPLL Freq Word (Fractional[15:8])12'd19 :cmd_data={1'b1,10'h041,8'h13};// BBPLL Freq Word (Fractional[23:16])12'd20 :cmd_data={1'b1,10'h044,8'h19};// BBPLL Freq Word (Integer[7:0])12'd21 :cmd_data={1'b1,10'h03f,8'h05};// Start BBPLL Calibration12'd22 :cmd_data={1'b1,10'h03f,8'h01};// Clear BBPLL start calibration bit12'd23 :cmd_data={1'b1,10'h04c,8'h86};// Increase BBPLL KV and phase margin12'd24 :cmd_data={1'b1,10'h04d,8'h01};// Increase BBPLL KV and phase margin12'd25 :cmd_data={1'b1,10'h04d,8'h05};// Increase BBPLL KV and phase margin12'd26 :cmd_data={1'b0,10'h05e,8'h00};//CALDONE12'd27 :cmd_data={1'b1,10'h002,8'hde};// Setup Tx Digital Filters/ Channels12'd28 :cmd_data={1'b1,10'h003,8'hde};// Setup Rx Digital Filters/ Channels12'd29 :cmd_data={1'b1,10'h004,8'h03};// Select Rx input pin(A,B,C)/ Tx out pin (A,B)12'd30 :cmd_data={1'b1,10'h00a,8'h02};// Set BBPLL post divide rate
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************12'd31 :cmd_data={1'b1,10'h010,8'hc8};// I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK12'd32 :cmd_data={1'b1,10'h011,8'h00};// I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data12'd33 :cmd_data={1'b1,10'h012,8'h02};// I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits12'd34 :cmd_data={1'b1,10'h006,8'h0f};// PPORT Rx Delay (adjusts Tco Dataclk->Data)12'd35 :cmd_data={1'b1,10'h007,8'h00};// PPORT TX Delay (adjusts setup/hold FBCLK->Data)
//************************************************************
// Setup AuxDAC
//************************************************************12'd36 : cmd_data={1'b1,10'h03C,8'h21};12'd37 : cmd_data={1'b1,10'h03D,8'h00};12'd38 : cmd_data={1'b1,10'h03E,8'h00};12'd39 :cmd_data={1'b1,10'h018,8'h00};// AuxDAC1 Word[9:2]12'd40 :cmd_data={1'b1,10'h019,8'h00};// AuxDAC2 Word[9:2]12'd41 :cmd_data={1'b1,10'h01a,8'h00};// AuxDAC1 Config and Word[1:0]12'd42 :cmd_data={1'b1,10'h01b,8'h00};// AuxDAC2 Config and Word[1:0]12'd43 :cmd_data={1'b1,10'h023,8'hff};// AuxDAC Manaul/Auto Control12'd44 :cmd_data={1'b1,10'h026,8'h00};// AuxDAC Manual Select Bit/GPO Manual Select12'd45 :cmd_data={1'b1,10'h030,8'h00};// AuxDAC1 Rx Delay12'd46 :cmd_data={1'b1,10'h031,8'h00};// AuxDAC1 Tx Delay12'd47 :cmd_data={1'b1,10'h032,8'h00};// AuxDAC2 Rx Delay12'd48 :cmd_data={1'b1,10'h033,8'h00};// AuxDAC2 Tx Delay
//************************************************************
// Setup AuxADC
//************************************************************12'd49 :cmd_data={1'b1,10'h00b,8'h00};// Temp Sensor Setup (Offset)12'd50 :cmd_data={1'b1,10'h00c,8'h00};// Temp Sensor Setup (Temp Window)12'd51 :cmd_data={1'b1,10'h00d,8'h03};// Temp Sensor Setup (Periodic Measure)12'd52 :cmd_data={1'b1,10'h00f,8'h04};// Temp Sensor Setup (Decimation)12'd53 :cmd_data={1'b1,10'h01c,8'h10};// AuxADC Setup (Clock Div)12'd54 :cmd_data={1'b1,10'h01d,8'h01};// AuxADC Setup (Decimation/Enable)
//************************************************************
// Setup Control Outs
//************************************************************12'd55 :cmd_data={1'b1,10'h035,8'h00};// Ctrl Out index12'd56 :cmd_data={1'b1,10'h036,8'hff};// Ctrl Out [7:0] output enable
//************************************************************
// Setup GPO
//************************************************************12'd57 :cmd_data={1'b1,10'h03a,8'h25};// Set number of REFCLK cycles for 1us delay timer12'd58 :cmd_data={1'b1,10'h020,8'h00};// GPO Auto Enable Setup in RX and TX12'd59 :cmd_data={1'b1,10'h027,8'h03};// GPO Manual and GPO auto value in ALERT12'd60 :cmd_data={1'b1,10'h028,8'h00};// GPO_0 RX Delay12'd61 :cmd_data={1'b1,10'h029,8'h00};// GPO_1 RX Delay12'd62 :cmd_data={1'b1,10'h02a,8'h00};// GPO_2 RX Delay12'd63 :cmd_data={1'b1,10'h02b,8'h00};// GPO_3 RX Delay12'd64 :cmd_data={1'b1,10'h02c,8'h00};// GPO_0 TX Delay12'd65 :cmd_data={1'b1,10'h02d,8'h00};// GPO_1 TX Delay12'd66 :cmd_data={1'b1,10'h02e,8'h00};// GPO_2 TX Delay12'd67 :cmd_data={1'b1,10'h02f,8'h00};// GPO_3 TX Delay
//************************************************************
// Setup RF PLL non-frequency-dependent registers
//************************************************************12'd68 :cmd_data={1'b1,10'h261,8'h00};// Set Rx LO Power mode12'd69 :cmd_data={1'b1,10'h2a1,8'h00};// Set Tx LO Power mode12'd70 :cmd_data={1'b1,10'h248,8'h0b};// Enable Rx VCO LDO12'd71 :cmd_data={1'b1,10'h288,8'h0b};// Enable Tx VCO LDO12'd72 :cmd_data={1'b1,10'h246,8'h02};// Set VCO Power down TCF bits12'd73 :cmd_data={1'b1,10'h286,8'h02};// Set VCO Power down TCF bits12'd74 :cmd_data={1'b1,10'h249,8'h8e};// Set VCO cal length12'd75 :cmd_data={1'b1,10'h289,8'h8e};// Set VCO cal length12'd76 :cmd_data={1'b1,10'h23b,8'h80};// Enable Rx VCO cal12'd77 :cmd_data={1'b1,10'h27b,8'h80};// Enable Tx VCO cal12'd78 :cmd_data={1'b1,10'h243,8'h0d};// Set Rx prescaler bias12'd79 :cmd_data={1'b1,10'h283,8'h0d};// Set Tx prescaler bias12'd80 :cmd_data={1'b1,10'h23d,8'h00};// Clear Half VCO cal clock setting12'd81 :cmd_data={1'b1,10'h27d,8'h00};// Clear Half VCO cal clock setting12'd82 :cmd_data={1'b1,10'h015,8'h0c};// Set Dual Synth mode bit12'd83 :cmd_data={1'b1,10'h014,8'h15};// Set Force ALERT State bit12'd84 :cmd_data={1'b1,10'h013,8'h01};// Set ENSM FDD mode12'd85 :cmd_data={1'b1,10'h23d,8'h04};// Start RX CP cal12'd86 :cmd_data={1'b0,10'h244,8'h00};//CALDONE12'd87 :cmd_data={1'b1,10'h27d,8'h04};// Start TX CP cal12'd88 :cmd_data={1'b0,10'h284,8'h00};//CALDONE12'd89 :cmd_data={1'b1,10'h23d,8'h00};// Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT12'd90 :cmd_data={1'b1,10'h27d,8'h00};// Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT
//************************************************************
// FDD RX,TX Synth Frequency: 2400.000000,2500.000000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************12'd91 :cmd_data={1'b1,10'h23a,8'h4a};// Set VCO Output level[3:0]12'd92 :cmd_data={1'b1,10'h239,8'hc0};// Set Init ALC Value[3:0] and VCO Varactor[3:0]12'd93 :cmd_data={1'b1,10'h242,8'h0d};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]12'd94 :cmd_data={1'b1,10'h238,8'h68};// Set VCO Cal Offset[3:0]12'd95 :cmd_data={1'b1,10'h245,8'h00};// Set VCO Cal Ref Tcf[2:0]12'd96 :cmd_data={1'b1,10'h251,8'h09};// Set VCO Varactor Reference[3:0]12'd97 :cmd_data={1'b1,10'h250,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]12'd98 :cmd_data={1'b1,10'h23b,8'h91};// Set Synth Loop Filter charge pump current (Icp)12'd99 :cmd_data={1'b1,10'h23e,8'hd4};// Set Synth Loop Filter C2 and C112'd100 :cmd_data={1'b1,10'h23f,8'hdf};// Set Synth Loop Filter R1 and C312'd101 :cmd_data={1'b1,10'h240,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************12'd102 :cmd_data={1'b1,10'h27a,8'h4a};// Set VCO Output level[3:0]12'd103 :cmd_data={1'b1,10'h279,8'hc0};// Set Init ALC Value[3:0] and VCO Varactor[3:0]12'd104 :cmd_data={1'b1,10'h282,8'h0d};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]12'd105 :cmd_data={1'b1,10'h278,8'h70};// Set VCO Cal Offset[3:0]12'd106 :cmd_data={1'b1,10'h285,8'h00};// Set VCO Cal Ref Tcf[2:0]12'd107 :cmd_data={1'b1,10'h291,8'h09};// Set VCO Varactor Reference[3:0]12'd108 :cmd_data={1'b1,10'h290,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]12'd109 :cmd_data={1'b1,10'h27b,8'h8f};// Set Synth Loop Filter charge pump current (Icp)12'd110 :cmd_data={1'b1,10'h27e,8'hd4};// Set Synth Loop Filter C2 and C112'd111 :cmd_data={1'b1,10'h27f,8'hdf};// Set Synth Loop Filter R1 and C312'd112 :cmd_data={1'b1,10'h280,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************12'd113 :cmd_data={1'b1,10'h233,8'h00};// Write Rx Synth Fractional Freq Word[7:0]12'd114 :cmd_data={1'b1,10'h234,8'h00};// Write Rx Synth Fractional Freq Word[15:8]12'd115 :cmd_data={1'b1,10'h235,8'h00};// Write Rx Synth Fractional Freq Word[22:16]12'd116 :cmd_data={1'b1,10'h232,8'h00};// Write Rx Synth Integer Freq Word[10:8]12'd117 :cmd_data={1'b1,10'h231,8'h7d};// Write Rx Synth Integer Freq Word[7:0]12'd118 :cmd_data={1'b1,10'h005,8'h11};// Set LO divider setting12'd119 :cmd_data={1'b1,10'h273,8'ha8};// Write Tx Synth Fractional Freq Word[7:0]12'd120 :cmd_data={1'b1,10'h274,8'haa};// Write Tx Synth Fractional Freq Word[15:8]12'd121 :cmd_data={1'b1,10'h275,8'h1a};// Write Tx Synth Fractional Freq Word[22:16]12'd122 :cmd_data={1'b1,10'h272,8'h00};// Write Tx Synth Integer Freq Word[10:8]12'd123 :cmd_data={1'b1,10'h271,8'h82};// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)12'd124 :cmd_data={1'b1,10'h005,8'h11};// Set LO divider setting12'd125 :cmd_data={1'b0,10'h247,8'h00};// Check RX RF PLL lock status (0x247[1]==1 is locked)12'd126 :cmd_data={1'b0,10'h287,8'h00};// Check TX RF PLL lock status (0x287[1]==1 is locked)
//************************************************************
// Program Mixer GM Sub-table
//************************************************************12'd127 :cmd_data={1'b1,10'h13f,8'h02};// Start Clock12'd128 :cmd_data={1'b1,10'h138,8'h0f};// Addr Table Index12'd129 :cmd_data={1'b1,10'h139,8'h78};// Gain12'd130 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd131 :cmd_data={1'b1,10'h13b,8'h00};// GM12'd132 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd133 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd134 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd135 :cmd_data={1'b1,10'h138,8'h0e};// Addr Table Index12'd136 :cmd_data={1'b1,10'h139,8'h74};// Gain12'd137 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd138 :cmd_data={1'b1,10'h13b,8'h0d};// GM12'd139 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd140 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd141 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd142 :cmd_data={1'b1,10'h138,8'h0d};// Addr Table Index12'd143 :cmd_data={1'b1,10'h139,8'h70};// Gain12'd144 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd145 :cmd_data={1'b1,10'h13b,8'h15};// GM12'd146 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd147 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd148 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd149 :cmd_data={1'b1,10'h138,8'h0c};// Addr Table Index12'd150 :cmd_data={1'b1,10'h139,8'h6c};// Gain12'd151 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd152 :cmd_data={1'b1,10'h13b,8'h1b};// GM12'd153 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd154 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd155 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd156 :cmd_data={1'b1,10'h138,8'h0b};// Addr Table Index12'd157 :cmd_data={1'b1,10'h139,8'h68};// Gain12'd158 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd159 :cmd_data={1'b1,10'h13b,8'h21};// GM12'd160 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd161 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd162 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd163 :cmd_data={1'b1,10'h138,8'h0a};// Addr Table Index12'd164 :cmd_data={1'b1,10'h139,8'h64};// Gain12'd165 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd166 :cmd_data={1'b1,10'h13b,8'h25};// GM12'd167 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd168 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd169 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd170 :cmd_data={1'b1,10'h138,8'h09};// Addr Table Index12'd171 :cmd_data={1'b1,10'h139,8'h60};// Gain12'd172 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd173 :cmd_data={1'b1,10'h13b,8'h29};// GM12'd174 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd175 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd176 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd177 :cmd_data={1'b1,10'h138,8'h08};// Addr Table Index12'd178 :cmd_data={1'b1,10'h139,8'h5c};// Gain12'd179 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd180 :cmd_data={1'b1,10'h13b,8'h2c};// GM12'd181 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd182 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd183 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd184 :cmd_data={1'b1,10'h138,8'h07};// Addr Table Index12'd185 :cmd_data={1'b1,10'h139,8'h58};// Gain12'd186 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd187 :cmd_data={1'b1,10'h13b,8'h2f};// GM12'd188 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd189 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd190 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd191 :cmd_data={1'b1,10'h138,8'h06};// Addr Table Index12'd192 :cmd_data={1'b1,10'h139,8'h54};// Gain12'd193 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd194 :cmd_data={1'b1,10'h13b,8'h31};// GM12'd195 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd196 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd197 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd198 :cmd_data={1'b1,10'h138,8'h05};// Addr Table Index12'd199 :cmd_data={1'b1,10'h139,8'h50};// Gain12'd200 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd201 :cmd_data={1'b1,10'h13b,8'h33};// GM12'd202 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd203 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd204 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd205 :cmd_data={1'b1,10'h138,8'h04};// Addr Table Index12'd206 :cmd_data={1'b1,10'h139,8'h4c};// Gain12'd207 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd208 :cmd_data={1'b1,10'h13b,8'h34};// GM12'd209 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd210 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd211 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd212 :cmd_data={1'b1,10'h138,8'h03};// Addr Table Index12'd213 :cmd_data={1'b1,10'h139,8'h48};// Gain12'd214 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd215 :cmd_data={1'b1,10'h13b,8'h35};// GM12'd216 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd217 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd218 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd219 :cmd_data={1'b1,10'h138,8'h02};// Addr Table Index12'd220 :cmd_data={1'b1,10'h139,8'h30};// Gain12'd221 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd222 :cmd_data={1'b1,10'h13b,8'h3a};// GM12'd223 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd224 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd225 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd226 :cmd_data={1'b1,10'h138,8'h01};// Addr Table Index12'd227 :cmd_data={1'b1,10'h139,8'h18};// Gain12'd228 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd229 :cmd_data={1'b1,10'h13b,8'h3d};// GM12'd230 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd231 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd232 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd233 :cmd_data={1'b1,10'h138,8'h00};// Addr Table Index12'd234 :cmd_data={1'b1,10'h139,8'h00};// Gain12'd235 :cmd_data={1'b1,10'h13a,8'h00};// Bias12'd236 :cmd_data={1'b1,10'h13b,8'h3e};// GM12'd237 :cmd_data={1'b1,10'h13f,8'h06};// Write Words12'd238 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd239 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd240 :cmd_data={1'b1,10'h13f,8'h02};// Clear Write Bit12'd241 :cmd_data={1'b1,10'h13c,8'h00};// Delay for 3 ADCCLK/16 clock cycles (Dummy Write)12'd242 :cmd_data={1'b1,10'h13c,8'h00};// Delay ~1us (Dummy Write)12'd243 :cmd_data={1'b1,10'h13f,8'h00};// Stop Clock
//************************************************************
// Program Rx Gain Tables with GainTable2300MHz.csv
//************************************************************12'd244 :cmd_data={1'b1,10'h137,8'h1a};// Start Gain Table Clock12'd245 :cmd_data={1'b1,10'h130,8'h00};// Gain Table Index12'd246 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd247 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd248 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd249 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd250 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd251 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd252 :cmd_data={1'b1,10'h130,8'h01};// Gain Table Index12'd253 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd254 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd255 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd256 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd257 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd258 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd259 :cmd_data={1'b1,10'h130,8'h02};// Gain Table Index12'd260 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd261 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd262 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd263 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd264 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd265 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd266 :cmd_data={1'b1,10'h130,8'h03};// Gain Table Index12'd267 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd268 :cmd_data={1'b1,10'h132,8'h01};// TIA & LPF Word12'd269 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd270 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd271 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd272 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd273 :cmd_data={1'b1,10'h130,8'h04};// Gain Table Index12'd274 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd275 :cmd_data={1'b1,10'h132,8'h02};// TIA & LPF Word12'd276 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd277 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd278 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd279 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd280 :cmd_data={1'b1,10'h130,8'h05};// Gain Table Index12'd281 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd282 :cmd_data={1'b1,10'h132,8'h03};// TIA & LPF Word12'd283 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd284 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd285 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd286 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd287 :cmd_data={1'b1,10'h130,8'h06};// Gain Table Index12'd288 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd289 :cmd_data={1'b1,10'h132,8'h04};// TIA & LPF Word12'd290 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd291 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd292 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd293 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd294 :cmd_data={1'b1,10'h130,8'h07};// Gain Table Index12'd295 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd296 :cmd_data={1'b1,10'h132,8'h05};// TIA & LPF Word12'd297 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd298 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd299 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd300 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd301 :cmd_data={1'b1,10'h130,8'h08};// Gain Table Index12'd302 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd303 :cmd_data={1'b1,10'h132,8'h03};// TIA & LPF Word12'd304 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd305 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd306 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd307 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd308 :cmd_data={1'b1,10'h130,8'h09};// Gain Table Index12'd309 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd310 :cmd_data={1'b1,10'h132,8'h04};// TIA & LPF Word12'd311 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd312 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd313 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd314 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd315 :cmd_data={1'b1,10'h130,8'h0a};// Gain Table Index12'd316 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd317 :cmd_data={1'b1,10'h132,8'h05};// TIA & LPF Word12'd318 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd319 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd320 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd321 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd322 :cmd_data={1'b1,10'h130,8'h0b};// Gain Table Index12'd323 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd324 :cmd_data={1'b1,10'h132,8'h06};// TIA & LPF Word12'd325 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd326 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd327 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd328 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd329 :cmd_data={1'b1,10'h130,8'h0c};// Gain Table Index12'd330 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd331 :cmd_data={1'b1,10'h132,8'h07};// TIA & LPF Word12'd332 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd333 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd334 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd335 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd336 :cmd_data={1'b1,10'h130,8'h0d};// Gain Table Index12'd337 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd338 :cmd_data={1'b1,10'h132,8'h08};// TIA & LPF Word12'd339 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd340 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd341 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd342 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd343 :cmd_data={1'b1,10'h130,8'h0e};// Gain Table Index12'd344 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd345 :cmd_data={1'b1,10'h132,8'h09};// TIA & LPF Word12'd346 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd347 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd348 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd349 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd350 :cmd_data={1'b1,10'h130,8'h0f};// Gain Table Index12'd351 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd352 :cmd_data={1'b1,10'h132,8'h0a};// TIA & LPF Word12'd353 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd354 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd355 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd356 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd357 :cmd_data={1'b1,10'h130,8'h10};// Gain Table Index12'd358 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd359 :cmd_data={1'b1,10'h132,8'h0b};// TIA & LPF Word12'd360 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd361 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd362 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd363 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd364 :cmd_data={1'b1,10'h130,8'h11};// Gain Table Index12'd365 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd366 :cmd_data={1'b1,10'h132,8'h0c};// TIA & LPF Word12'd367 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd368 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd369 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd370 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd371 :cmd_data={1'b1,10'h130,8'h12};// Gain Table Index12'd372 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd373 :cmd_data={1'b1,10'h132,8'h0d};// TIA & LPF Word12'd374 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd375 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd376 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd377 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd378 :cmd_data={1'b1,10'h130,8'h13};// Gain Table Index12'd379 :cmd_data={1'b1,10'h131,8'h01};// Ext LNA, Int LNA, & Mixer Gain Word12'd380 :cmd_data={1'b1,10'h132,8'h0e};// TIA & LPF Word12'd381 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd382 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd383 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd384 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd385 :cmd_data={1'b1,10'h130,8'h14};// Gain Table Index12'd386 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd387 :cmd_data={1'b1,10'h132,8'h09};// TIA & LPF Word12'd388 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd389 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd390 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd391 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd392 :cmd_data={1'b1,10'h130,8'h15};// Gain Table Index12'd393 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd394 :cmd_data={1'b1,10'h132,8'h0a};// TIA & LPF Word12'd395 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd396 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd397 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd398 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd399 :cmd_data={1'b1,10'h130,8'h16};// Gain Table Index12'd400 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd401 :cmd_data={1'b1,10'h132,8'h0b};// TIA & LPF Word12'd402 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd403 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd404 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd405 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd406 :cmd_data={1'b1,10'h130,8'h17};// Gain Table Index12'd407 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd408 :cmd_data={1'b1,10'h132,8'h0c};// TIA & LPF Word12'd409 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd410 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd411 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd412 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd413 :cmd_data={1'b1,10'h130,8'h18};// Gain Table Index12'd414 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd415 :cmd_data={1'b1,10'h132,8'h0d};// TIA & LPF Word12'd416 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd417 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd418 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd419 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd420 :cmd_data={1'b1,10'h130,8'h19};// Gain Table Index12'd421 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd422 :cmd_data={1'b1,10'h132,8'h0e};// TIA & LPF Word12'd423 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd424 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd425 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd426 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd427 :cmd_data={1'b1,10'h130,8'h1a};// Gain Table Index12'd428 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd429 :cmd_data={1'b1,10'h132,8'h0f};// TIA & LPF Word12'd430 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd431 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd432 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd433 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd434 :cmd_data={1'b1,10'h130,8'h1b};// Gain Table Index12'd435 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd436 :cmd_data={1'b1,10'h132,8'h10};// TIA & LPF Word12'd437 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd438 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd439 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd440 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd441 :cmd_data={1'b1,10'h130,8'h1c};// Gain Table Index12'd442 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd443 :cmd_data={1'b1,10'h132,8'h2b};// TIA & LPF Word12'd444 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd445 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd446 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd447 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd448 :cmd_data={1'b1,10'h130,8'h1d};// Gain Table Index12'd449 :cmd_data={1'b1,10'h131,8'h02};// Ext LNA, Int LNA, & Mixer Gain Word12'd450 :cmd_data={1'b1,10'h132,8'h2c};// TIA & LPF Word12'd451 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd452 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd453 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd454 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd455 :cmd_data={1'b1,10'h130,8'h1e};// Gain Table Index12'd456 :cmd_data={1'b1,10'h131,8'h04};// Ext LNA, Int LNA, & Mixer Gain Word12'd457 :cmd_data={1'b1,10'h132,8'h27};// TIA & LPF Word12'd458 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd459 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd460 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd461 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd462 :cmd_data={1'b1,10'h130,8'h1f};// Gain Table Index12'd463 :cmd_data={1'b1,10'h131,8'h04};// Ext LNA, Int LNA, & Mixer Gain Word12'd464 :cmd_data={1'b1,10'h132,8'h28};// TIA & LPF Word12'd465 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd466 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd467 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd468 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd469 :cmd_data={1'b1,10'h130,8'h20};// Gain Table Index12'd470 :cmd_data={1'b1,10'h131,8'h04};// Ext LNA, Int LNA, & Mixer Gain Word12'd471 :cmd_data={1'b1,10'h132,8'h29};// TIA & LPF Word12'd472 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd473 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd474 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd475 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd476 :cmd_data={1'b1,10'h130,8'h21};// Gain Table Index12'd477 :cmd_data={1'b1,10'h131,8'h04};// Ext LNA, Int LNA, & Mixer Gain Word12'd478 :cmd_data={1'b1,10'h132,8'h2a};// TIA & LPF Word12'd479 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd480 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd481 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd482 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd483 :cmd_data={1'b1,10'h130,8'h22};// Gain Table Index12'd484 :cmd_data={1'b1,10'h131,8'h04};// Ext LNA, Int LNA, & Mixer Gain Word12'd485 :cmd_data={1'b1,10'h132,8'h2b};// TIA & LPF Word12'd486 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd487 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd488 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd489 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd490 :cmd_data={1'b1,10'h130,8'h23};// Gain Table Index12'd491 :cmd_data={1'b1,10'h131,8'h24};// Ext LNA, Int LNA, & Mixer Gain Word12'd492 :cmd_data={1'b1,10'h132,8'h21};// TIA & LPF Word12'd493 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd494 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd495 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd496 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd497 :cmd_data={1'b1,10'h130,8'h24};// Gain Table Index12'd498 :cmd_data={1'b1,10'h131,8'h24};// Ext LNA, Int LNA, & Mixer Gain Word12'd499 :cmd_data={1'b1,10'h132,8'h22};// TIA & LPF Word12'd500 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd501 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd502 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd503 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd504 :cmd_data={1'b1,10'h130,8'h25};// Gain Table Index12'd505 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd506 :cmd_data={1'b1,10'h132,8'h20};// TIA & LPF Word12'd507 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd508 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd509 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd510 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd511 :cmd_data={1'b1,10'h130,8'h26};// Gain Table Index12'd512 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd513 :cmd_data={1'b1,10'h132,8'h21};// TIA & LPF Word12'd514 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd515 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd516 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd517 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd518 :cmd_data={1'b1,10'h130,8'h27};// Gain Table Index12'd519 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd520 :cmd_data={1'b1,10'h132,8'h22};// TIA & LPF Word12'd521 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd522 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd523 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd524 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd525 :cmd_data={1'b1,10'h130,8'h28};// Gain Table Index12'd526 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd527 :cmd_data={1'b1,10'h132,8'h23};// TIA & LPF Word12'd528 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd529 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd530 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd531 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd532 :cmd_data={1'b1,10'h130,8'h29};// Gain Table Index12'd533 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd534 :cmd_data={1'b1,10'h132,8'h24};// TIA & LPF Word12'd535 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd536 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd537 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd538 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd539 :cmd_data={1'b1,10'h130,8'h2a};// Gain Table Index12'd540 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd541 :cmd_data={1'b1,10'h132,8'h25};// TIA & LPF Word12'd542 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd543 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd544 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd545 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd546 :cmd_data={1'b1,10'h130,8'h2b};// Gain Table Index12'd547 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd548 :cmd_data={1'b1,10'h132,8'h26};// TIA & LPF Word12'd549 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd550 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd551 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd552 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd553 :cmd_data={1'b1,10'h130,8'h2c};// Gain Table Index12'd554 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd555 :cmd_data={1'b1,10'h132,8'h27};// TIA & LPF Word12'd556 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd557 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd558 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd559 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd560 :cmd_data={1'b1,10'h130,8'h2d};// Gain Table Index12'd561 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd562 :cmd_data={1'b1,10'h132,8'h28};// TIA & LPF Word12'd563 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd564 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd565 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd566 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd567 :cmd_data={1'b1,10'h130,8'h2e};// Gain Table Index12'd568 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd569 :cmd_data={1'b1,10'h132,8'h29};// TIA & LPF Word12'd570 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd571 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd572 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd573 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd574 :cmd_data={1'b1,10'h130,8'h2f};// Gain Table Index12'd575 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd576 :cmd_data={1'b1,10'h132,8'h2a};// TIA & LPF Word12'd577 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd578 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd579 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd580 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd581 :cmd_data={1'b1,10'h130,8'h30};// Gain Table Index12'd582 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd583 :cmd_data={1'b1,10'h132,8'h2b};// TIA & LPF Word12'd584 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd585 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd586 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd587 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd588 :cmd_data={1'b1,10'h130,8'h31};// Gain Table Index12'd589 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd590 :cmd_data={1'b1,10'h132,8'h2c};// TIA & LPF Word12'd591 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd592 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd593 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd594 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd595 :cmd_data={1'b1,10'h130,8'h32};// Gain Table Index12'd596 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd597 :cmd_data={1'b1,10'h132,8'h2d};// TIA & LPF Word12'd598 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd599 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd600 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd601 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd602 :cmd_data={1'b1,10'h130,8'h33};// Gain Table Index12'd603 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd604 :cmd_data={1'b1,10'h132,8'h2e};// TIA & LPF Word12'd605 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd606 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd607 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd608 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd609 :cmd_data={1'b1,10'h130,8'h34};// Gain Table Index12'd610 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd611 :cmd_data={1'b1,10'h132,8'h2f};// TIA & LPF Word12'd612 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd613 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd614 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd615 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd616 :cmd_data={1'b1,10'h130,8'h35};// Gain Table Index12'd617 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd618 :cmd_data={1'b1,10'h132,8'h30};// TIA & LPF Word12'd619 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd620 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd621 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd622 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd623 :cmd_data={1'b1,10'h130,8'h36};// Gain Table Index12'd624 :cmd_data={1'b1,10'h131,8'h44};// Ext LNA, Int LNA, & Mixer Gain Word12'd625 :cmd_data={1'b1,10'h132,8'h31};// TIA & LPF Word12'd626 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd627 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd628 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd629 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd630 :cmd_data={1'b1,10'h130,8'h37};// Gain Table Index12'd631 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd632 :cmd_data={1'b1,10'h132,8'h2e};// TIA & LPF Word12'd633 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd634 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd635 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd636 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd637 :cmd_data={1'b1,10'h130,8'h38};// Gain Table Index12'd638 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd639 :cmd_data={1'b1,10'h132,8'h2f};// TIA & LPF Word12'd640 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd641 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd642 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd643 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd644 :cmd_data={1'b1,10'h130,8'h39};// Gain Table Index12'd645 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd646 :cmd_data={1'b1,10'h132,8'h30};// TIA & LPF Word12'd647 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd648 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd649 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd650 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd651 :cmd_data={1'b1,10'h130,8'h3a};// Gain Table Index12'd652 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd653 :cmd_data={1'b1,10'h132,8'h31};// TIA & LPF Word12'd654 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd655 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd656 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd657 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd658 :cmd_data={1'b1,10'h130,8'h3b};// Gain Table Index12'd659 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd660 :cmd_data={1'b1,10'h132,8'h32};// TIA & LPF Word12'd661 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd662 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd663 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd664 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd665 :cmd_data={1'b1,10'h130,8'h3c};// Gain Table Index12'd666 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd667 :cmd_data={1'b1,10'h132,8'h33};// TIA & LPF Word12'd668 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd669 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd670 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd671 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd672 :cmd_data={1'b1,10'h130,8'h3d};// Gain Table Index12'd673 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd674 :cmd_data={1'b1,10'h132,8'h34};// TIA & LPF Word12'd675 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd676 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd677 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd678 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd679 :cmd_data={1'b1,10'h130,8'h3e};// Gain Table Index12'd680 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd681 :cmd_data={1'b1,10'h132,8'h35};// TIA & LPF Word12'd682 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd683 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd684 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd685 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd686 :cmd_data={1'b1,10'h130,8'h3f};// Gain Table Index12'd687 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd688 :cmd_data={1'b1,10'h132,8'h36};// TIA & LPF Word12'd689 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd690 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd691 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd692 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd693 :cmd_data={1'b1,10'h130,8'h40};// Gain Table Index12'd694 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd695 :cmd_data={1'b1,10'h132,8'h37};// TIA & LPF Word12'd696 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd697 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd698 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd699 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd700 :cmd_data={1'b1,10'h130,8'h41};// Gain Table Index12'd701 :cmd_data={1'b1,10'h131,8'h64};// Ext LNA, Int LNA, & Mixer Gain Word12'd702 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd703 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd704 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd705 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd706 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd707 :cmd_data={1'b1,10'h130,8'h42};// Gain Table Index12'd708 :cmd_data={1'b1,10'h131,8'h65};// Ext LNA, Int LNA, & Mixer Gain Word12'd709 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd710 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd711 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd712 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd713 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd714 :cmd_data={1'b1,10'h130,8'h43};// Gain Table Index12'd715 :cmd_data={1'b1,10'h131,8'h66};// Ext LNA, Int LNA, & Mixer Gain Word12'd716 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd717 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd718 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd719 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd720 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd721 :cmd_data={1'b1,10'h130,8'h44};// Gain Table Index12'd722 :cmd_data={1'b1,10'h131,8'h67};// Ext LNA, Int LNA, & Mixer Gain Word12'd723 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd724 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd725 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd726 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd727 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd728 :cmd_data={1'b1,10'h130,8'h45};// Gain Table Index12'd729 :cmd_data={1'b1,10'h131,8'h68};// Ext LNA, Int LNA, & Mixer Gain Word12'd730 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd731 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd732 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd733 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd734 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd735 :cmd_data={1'b1,10'h130,8'h46};// Gain Table Index12'd736 :cmd_data={1'b1,10'h131,8'h69};// Ext LNA, Int LNA, & Mixer Gain Word12'd737 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd738 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd739 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd740 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd741 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd742 :cmd_data={1'b1,10'h130,8'h47};// Gain Table Index12'd743 :cmd_data={1'b1,10'h131,8'h6a};// Ext LNA, Int LNA, & Mixer Gain Word12'd744 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd745 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd746 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd747 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd748 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd749 :cmd_data={1'b1,10'h130,8'h48};// Gain Table Index12'd750 :cmd_data={1'b1,10'h131,8'h6b};// Ext LNA, Int LNA, & Mixer Gain Word12'd751 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd752 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd753 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd754 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd755 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd756 :cmd_data={1'b1,10'h130,8'h49};// Gain Table Index12'd757 :cmd_data={1'b1,10'h131,8'h6c};// Ext LNA, Int LNA, & Mixer Gain Word12'd758 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd759 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd760 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd761 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd762 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd763 :cmd_data={1'b1,10'h130,8'h4a};// Gain Table Index12'd764 :cmd_data={1'b1,10'h131,8'h6d};// Ext LNA, Int LNA, & Mixer Gain Word12'd765 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd766 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd767 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd768 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd769 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd770 :cmd_data={1'b1,10'h130,8'h4b};// Gain Table Index12'd771 :cmd_data={1'b1,10'h131,8'h6e};// Ext LNA, Int LNA, & Mixer Gain Word12'd772 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd773 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd774 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd775 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd776 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd777 :cmd_data={1'b1,10'h130,8'h4c};// Gain Table Index12'd778 :cmd_data={1'b1,10'h131,8'h6f};// Ext LNA, Int LNA, & Mixer Gain Word12'd779 :cmd_data={1'b1,10'h132,8'h38};// TIA & LPF Word12'd780 :cmd_data={1'b1,10'h133,8'h20};// DC Cal bit & Dig Gain Word12'd781 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd782 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd783 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd784 :cmd_data={1'b1,10'h130,8'h4d};// Gain Table Index12'd785 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd786 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd787 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd788 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd789 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd790 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd791 :cmd_data={1'b1,10'h130,8'h4e};// Gain Table Index12'd792 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd793 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd794 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd795 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd796 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd797 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd798 :cmd_data={1'b1,10'h130,8'h4f};// Gain Table Index12'd799 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd800 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd801 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd802 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd803 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd804 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd805 :cmd_data={1'b1,10'h130,8'h50};// Gain Table Index12'd806 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd807 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd808 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd809 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd810 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd811 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd812 :cmd_data={1'b1,10'h130,8'h51};// Gain Table Index12'd813 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd814 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd815 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd816 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd817 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd818 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd819 :cmd_data={1'b1,10'h130,8'h52};// Gain Table Index12'd820 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd821 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd822 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd823 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd824 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd825 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd826 :cmd_data={1'b1,10'h130,8'h53};// Gain Table Index12'd827 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd828 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd829 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd830 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd831 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd832 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd833 :cmd_data={1'b1,10'h130,8'h54};// Gain Table Index12'd834 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd835 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd836 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd837 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd838 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd839 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd840 :cmd_data={1'b1,10'h130,8'h55};// Gain Table Index12'd841 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd842 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd843 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd844 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd845 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd846 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd847 :cmd_data={1'b1,10'h130,8'h56};// Gain Table Index12'd848 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd849 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd850 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd851 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd852 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd853 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd854 :cmd_data={1'b1,10'h130,8'h57};// Gain Table Index12'd855 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd856 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd857 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd858 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd859 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd860 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd861 :cmd_data={1'b1,10'h130,8'h58};// Gain Table Index12'd862 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd863 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd864 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd865 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd866 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd867 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd868 :cmd_data={1'b1,10'h130,8'h59};// Gain Table Index12'd869 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd870 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd871 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd872 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd873 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd874 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd875 :cmd_data={1'b1,10'h130,8'h5a};// Gain Table Index12'd876 :cmd_data={1'b1,10'h131,8'h00};// Ext LNA, Int LNA, & Mixer Gain Word12'd877 :cmd_data={1'b1,10'h132,8'h00};// TIA & LPF Word12'd878 :cmd_data={1'b1,10'h133,8'h00};// DC Cal bit & Dig Gain Word12'd879 :cmd_data={1'b1,10'h137,8'h1e};// Write Words12'd880 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay 3 ADCCLK/16 cycles12'd881 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd882 :cmd_data={1'b1,10'h137,8'h1a};// Clear Write Bit12'd883 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd884 :cmd_data={1'b1,10'h134,8'h00};// Dummy Write to delay ~1us12'd885 :cmd_data={1'b1,10'h137,8'h00};// Stop Gain Table Clock
//************************************************************
// Setup Rx Manual Gain Registers
//************************************************************12'd886 :cmd_data={1'b1,10'h0fa,8'he0};// Gain Control Mode Select12'd887 :cmd_data={1'b1,10'h0fb,8'h08};// Table, Digital Gain, Man Gain Ctrl12'd888 :cmd_data={1'b1,10'h0fc,8'h23};// Incr Step Size, ADC Overrange Size12'd889 :cmd_data={1'b1,10'h0fd,8'h4c};// Max Full/LMT Gain Table Index12'd890 :cmd_data={1'b1,10'h0fe,8'h44};// Decr Step Size, Peak Overload Time12'd891 :cmd_data={1'b1,10'h100,8'h6f};// Max Digital Gain12'd892 :cmd_data={1'b1,10'h104,8'h2f};// ADC Small Overload Threshold12'd893 :cmd_data={1'b1,10'h105,8'h3a};// ADC Large Overload Threshold12'd894 :cmd_data={1'b1,10'h107,8'h2b};// Small LMT Overload Threshold12'd895 :cmd_data={1'b1,10'h108,8'h31};// Large LMT Overload Threshold12'd896 :cmd_data={1'b1,10'h109,8'h4c};// Rx1 Full/LMT Gain Index12'd897 :cmd_data={1'b1,10'h10a,8'hf8};// Rx1 LPF Gain Index12'd898 :cmd_data={1'b1,10'h10b,8'h00};// Rx1 Digital Gain Index12'd899 :cmd_data={1'b1,10'h10c,8'h4c};// Rx2 Full/LMT Gain Index12'd900 :cmd_data={1'b1,10'h10d,8'h18};// Rx2 LPF Gain Index12'd901 :cmd_data={1'b1,10'h10e,8'h00};// Rx2 Digital Gain Index12'd902 :cmd_data={1'b1,10'h114,8'h30};// Low Power Threshold12'd903 :cmd_data={1'b1,10'h11a,8'h1c};// Initial LMT Gain Limit12'd904 :cmd_data={1'b1,10'h081,8'h00};// Tx Symbol Gain Control
//************************************************************
// RX Baseband Filter Tuning (Real BW: 4.500000 MHz) 3dB Filter
// Corner @ 6.300000 MHz)
//************************************************************12'd905 :cmd_data={1'b1,10'h1fb,8'h04};// RX Freq Corner (MHz)12'd906 :cmd_data={1'b1,10'h1fc,8'h40};// RX Freq Corner (Khz)12'd907 :cmd_data={1'b1,10'h1f8,8'h12};// Rx BBF Tune Divider[7:0]12'd908 :cmd_data={1'b1,10'h1f9,8'h1e};// RX BBF Tune Divider[8]12'd909 :cmd_data={1'b1,10'h1d5,8'h3f};// Set Rx Mix LO CM12'd910 :cmd_data={1'b1,10'h1c0,8'h03};// Set GM common mode12'd911 :cmd_data={1'b1,10'h1e2,8'h02};// Enable Rx1 Filter Tuner 12'd912 :cmd_data={1'b1,10'h1e3,8'h02};// Enable Rx2 Filter Tuner 12'd913 :cmd_data={1'b1,10'h016,8'h80};// Start RX Filter Tune12'd914 :cmd_data={1'b0,10'h016,8'h00};//CALDONE12'd915 :cmd_data={1'b1,10'h1e2,8'h03};// Disable Rx Filter Tuner (Rx1)12'd916 :cmd_data={1'b1,10'h1e3,8'h03};// Disable Rx Filter Tuner (Rx2)
//************************************************************
// TX Baseband Filter Tuning (Real BW: 4.500000 MHz) 3dB Filter
// Corner @ 7.200000 MHz)
//************************************************************12'd917 :cmd_data={1'b1,10'h0d6,8'h10};// TX BBF Tune Divider[7:0]12'd918 :cmd_data={1'b1,10'h0d7,8'h1e};// TX BBF Tune Divider[8]12'd919 :cmd_data={1'b1,10'h0ca,8'h22};// Enable Tx Filter Tuner12'd920 :cmd_data={1'b1,10'h016,8'h40};// Start Tx Filter Tune12'd921 :cmd_data={1'b0,10'h016,8'h00};//CALDONE12'd922 :cmd_data={1'b1,10'h0ca,8'h26};// Disable Tx Filter Tuner (Both Channels)
//************************************************************
// RX TIA Setup: Setup values scale based on RxBBF calibration
// results. See information in Calibration Guide.
//************************************************************12'd923 :cmd_data={1'b0,10'h1eb,8'h00};// Read RXBBF C3(MSB)12'd924 :cmd_data={1'b0,10'h1ec,8'h00};// Read RXBBF C3(LSB)12'd925 :cmd_data={1'b0,10'h1e6,8'h00};// Read RXBBF R234612'd926 :cmd_data={1'b1,10'h1db,8'h60};// Set TIA selcc[2:0]12'd927 :cmd_data={1'b1,10'h1dd,8'h0a};// Set RX TIA1 C MSB[6:0]12'd928 :cmd_data={1'b1,10'h1df,8'h0a};// Set RX TIA2 C MSB[6:0]12'd929 :cmd_data={1'b1,10'h1dc,8'h40};// Set RX TIA1 C LSB[5:0]12'd930 :cmd_data={1'b1,10'h1de,8'h40};// Set RX TIA2 C LSB[5:0]
//************************************************************
// TX Secondary Filter Calibration Setup: Real Bandwidth
// 4.500000MHz, 3dB Corner @ 22.500000MHz
//************************************************************12'd931 :cmd_data={1'b1,10'h0d2,8'h3b};// TX Secondary Filter PDF Cap cal[5:0]12'd932 :cmd_data={1'b1,10'h0d1,8'h0c};// TX Secondary Filter PDF Res cal[3:0]12'd933 :cmd_data={1'b1,10'h0d0,8'h59};// Pdampbias
//************************************************************
// ADC Setup: Tune ADC Performance based on RX analog filter tune
// corner. Real Bandwidth: 4.303445 MHz, ADC Clock Frequency:
// 245.760000 MHz. The values in registers 0x200 - 0x227 need to be
// calculated using the equations in the Calibration Guide.
//************************************************************12'd934 :cmd_data={1'b0,10'h1eb,8'h00};// Read RxBBF C3 MSB after calibration12'd935 :cmd_data={1'b0,10'h1ec,8'h00};// Read RxBBF C3 LSB after calibration12'd936 :cmd_data={1'b0,10'h1e6,8'h00};// Read RxBBF R3 after calibration12'd937 :cmd_data={1'b1,10'h200,8'h00};12'd938 :cmd_data={1'b1,10'h201,8'h00};12'd939 :cmd_data={1'b1,10'h202,8'h00};12'd940 :cmd_data={1'b1,10'h203,8'h24};12'd941 :cmd_data={1'b1,10'h204,8'h24};12'd942 :cmd_data={1'b1,10'h205,8'h00};12'd943 :cmd_data={1'b1,10'h206,8'h00};12'd944 :cmd_data={1'b1,10'h207,8'h7c};12'd945 :cmd_data={1'b1,10'h208,8'h53};12'd946 :cmd_data={1'b1,10'h209,8'h3c};12'd947 :cmd_data={1'b1,10'h20a,8'h4b};12'd948 :cmd_data={1'b1,10'h20b,8'h34};12'd949 :cmd_data={1'b1,10'h20c,8'h4e};12'd950 :cmd_data={1'b1,10'h20d,8'h32};12'd951 :cmd_data={1'b1,10'h20e,8'h00};12'd952 :cmd_data={1'b1,10'h20f,8'h7f};12'd953 :cmd_data={1'b1,10'h210,8'h7f};12'd954 :cmd_data={1'b1,10'h211,8'h7f};12'd955 :cmd_data={1'b1,10'h212,8'h49};12'd956 :cmd_data={1'b1,10'h213,8'h49};12'd957 :cmd_data={1'b1,10'h214,8'h49};12'd958 :cmd_data={1'b1,10'h215,8'h4c};12'd959 :cmd_data={1'b1,10'h216,8'h4c};12'd960 :cmd_data={1'b1,10'h217,8'h4c};12'd961 :cmd_data={1'b1,10'h218,8'h2e};12'd962 :cmd_data={1'b1,10'h219,8'h98};12'd963 :cmd_data={1'b1,10'h21a,8'h1b};12'd964 :cmd_data={1'b1,10'h21b,8'h13};12'd965 :cmd_data={1'b1,10'h21c,8'h98};12'd966 :cmd_data={1'b1,10'h21d,8'h1b};12'd967 :cmd_data={1'b1,10'h21e,8'h13};12'd968 :cmd_data={1'b1,10'h21f,8'h98};12'd969 :cmd_data={1'b1,10'h220,8'h1b};12'd970 :cmd_data={1'b1,10'h221,8'h27};12'd971 :cmd_data={1'b1,10'h222,8'h27};12'd972 :cmd_data={1'b1,10'h223,8'h40};12'd973 :cmd_data={1'b1,10'h224,8'h40};12'd974 :cmd_data={1'b1,10'h225,8'h2c};12'd975 :cmd_data={1'b1,10'h226,8'h00};12'd976 :cmd_data={1'b1,10'h227,8'h00};
//************************************************************
// Setup and Run BB DC and RF DC Offset Calibrations
//************************************************************12'd977 :cmd_data={1'b1,10'h193,8'h3f};12'd978 :cmd_data={1'b1,10'h190,8'h0f};// Set BBDC tracking shift M value, only applies when BB DC tracking enabled12'd979 :cmd_data={1'b1,10'h194,8'h01};// BBDC Cal setting12'd980 :cmd_data={1'b1,10'h016,8'h01};// Start BBDC offset cal12'd981 :cmd_data={1'b0,10'h016,8'h00};//CALDONE12'd982 :cmd_data={1'b1,10'h185,8'h20};// Set RF DC offset Wait Count12'd983 :cmd_data={1'b1,10'h186,8'h32};// Set RF DC Offset Count[7:0]12'd984 :cmd_data={1'b1,10'h187,8'h24};// Settings for RF DC cal12'd985 :cmd_data={1'b1,10'h18b,8'h83};// Settings for RF DC cal12'd986 :cmd_data={1'b1,10'h188,8'h05};// Settings for RF DC cal12'd987 :cmd_data={1'b1,10'h189,8'h30};// Settings for RF DC cal12'd988 :cmd_data={1'b1,10'h016,8'h02};// Start RFDC offset cal
//************************************************************
// Tx Quadrature Calibration Settings
//************************************************************12'd989 :cmd_data={1'b0,10'h0a3,8'h00};// Masked Read: Read lower 6 bits, overwrite [7:6] below12'd990 :cmd_data={1'b1,10'h0a0,8'h15};// Set TxQuadcal NCO frequency12'd991 :cmd_data={1'b1,10'h0a3,8'h00};// Set TxQuadcal NCO frequency (Only update bits [7:6])12'd992 :cmd_data={1'b1,10'h0a1,8'h7b};// Tx Quad Cal Configuration, Phase and Gain Cal Enable12'd993 :cmd_data={1'b1,10'h0a9,8'hff};// Set Tx Quad Cal Count12'd994 :cmd_data={1'b1,10'h0a2,8'h7f};// Set Tx Quad Cal Kexp12'd995 :cmd_data={1'b1,10'h0a5,8'h01};// Set Tx Quad Cal Magnitude Threshhold12'd996 :cmd_data={1'b1,10'h0a6,8'h01};// Set Tx Quad Cal Magnitude Threshhold12'd997 :cmd_data={1'b1,10'h0aa,8'h25};// Set Tx Quad Cal Gain Table index12'd998 :cmd_data={1'b1,10'h0a4,8'hf0};// Set Tx Quad Cal Settle Count12'd999 :cmd_data={1'b1,10'h0ae,8'h00};// Set Tx Quad Cal LPF Gain index incase Split table mode used12'd1000 :cmd_data={1'b1,10'h169,8'hc0};// Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration12'd1001 :cmd_data={1'b1,10'h016,8'h10};// Start Tx Quad cal12'd1002 :cmd_data={1'b0,10'h016,8'h00};//CALDONE12'd1003 :cmd_data={1'b1,10'h16a,8'h75};// Set Kexp Phase12'd1004 :cmd_data={1'b1,10'h16b,8'h95};// Set Kexp Amplitude & Prevent Positive Gain Bit12'd1005 :cmd_data={1'b1,10'h169,8'hcf};// Enable Rx Quadrature Calibration Tracking12'd1006 :cmd_data={1'b1,10'h18b,8'had};// Enable BB and RF DC Tracking Calibrations12'd1007 :cmd_data={1'b1,10'h012,8'h02};// Cals done, Set PPORT Config12'd1008 :cmd_data={1'b1,10'h013,8'h01};// Set ENSM FDD/TDD bit12'd1009 :cmd_data={1'b1,10'h015,8'h0c};// Set Dual Synth Mode, FDD External Control bits properly
//************************************************************
// Set Tx Attenuation: Tx1: 10.00 dB, Tx2: 10.00 dB
//************************************************************12'd1010 :cmd_data={1'b1,10'h073,8'h28};12'd1011 :cmd_data={1'b1,10'h074,8'h00};12'd1012 :cmd_data={1'b1,10'h075,8'h28};12'd1013 :cmd_data={1'b1,10'h076,8'h00};
//************************************************************
// Setup RSSI and Power Measurement Duration Registers
//************************************************************12'd1014 :cmd_data={1'b1,10'h150,8'h0e};// RSSI Measurement Duration 0, 112'd1015 :cmd_data={1'b1,10'h151,8'h00};// RSSI Measurement Duration 2, 312'd1016 :cmd_data={1'b1,10'h152,8'hff};// RSSI Weighted Multiplier 012'd1017 :cmd_data={1'b1,10'h153,8'h00};// RSSI Weighted Multiplier 112'd1018 :cmd_data={1'b1,10'h154,8'h00};// RSSI Weighted Multiplier 212'd1019 :cmd_data={1'b1,10'h155,8'h00};// RSSI Weighted Multiplier 312'd1020 :cmd_data={1'b1,10'h156,8'h00};// RSSI Delay12'd1021 :cmd_data={1'b1,10'h157,8'h00};// RSSI Wait12'd1022 :cmd_data={1'b1,10'h158,8'h0d};// RSSI Mode Select12'd1023 :cmd_data={1'b1,10'h15c,8'h67};// Power Measurement Durationendcaseend
endfunction加载配置SPI指令 和ADC DAC 接口
AD9361(.clk_40m(clk_40m ),//40MHz.clk_110m(ad9361_l_clk ),//110M.SD_I_9361(SD_I_9361 ),.RSTB_9361(RSTB_9361 ),.SCLK_9361_o(SCLK_9361_o ),.CS_9361_o(CS_9361_o ), .SD_O_9361_o(SD_O_9361_o ),.rx_clk_in_p(rx_clk_in_p ),.rx_clk_in_n(rx_clk_in_n ),.rx_frame_in_p(rx_frame_in_p ),.rx_frame_in_n(rx_frame_in_n ),.rx_data_in_p(rx_data_in_p ),.rx_data_in_n(rx_data_in_n ),.tx_clk_out_p(tx_clk_out_p ),.tx_clk_out_n(tx_clk_out_n ),.tx_frame_out_p(tx_frame_out_p ),.tx_frame_out_n(tx_frame_out_n ),.tx_data_out_p(tx_data_out_p ),.tx_data_out_n(tx_data_out_n ),.ad9361_l_clk(ad9361_l_clk_2 ),.rst( ),.dout_bpsk(dout_i ), .dout_bpsk_q(dout_q ),.adc_i0(adc_i0 ),.adc_q0(adc_q0 ),.adc_i1( ),.adc_q1( ), .ENABLE_9361(ENABLE_AD9361 ),.TXNRX_9361(TXNRX )
);
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