本文主要是介绍实现3x3卷积的手写FIFO，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
例子来自米联科例程，
因为不同平台之间调IP会变麻烦，重新阅读手册太花时间了（虽然我觉得fifo这种常用IP尽量掌握为好），使用手写的FIFO可以节约开发的流程。
通过这个例子也可以优化自己所使用的手写FIFO。
// by CrazyBird
module Line_Shift_RAM_8Bit
#(parameter DATA_WIDTH = 8 ,parameter ADDR_WIDTH = 11 ,parameter DATA_DEPTH = 1280 ,parameter DELAY_NUM = 0
)(input wire clk ,input wire rst_n ,input wire clken ,input wire [DATA_WIDTH-1:0] din , output wire [DATA_WIDTH-1:0] dout
);
//----------------------------------------------------------------------
localparam BRAM_DEPTH = DATA_DEPTH + 1;
localparam INIT_ADDR = DATA_DEPTH - DELAY_NUM;//----------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] bram_waddr;
reg [ADDR_WIDTH-1:0] bram_raddr;always @(posedge clk or negedge rst_n)
beginif(rst_n == 1'b0)beginbram_waddr <= INIT_ADDR;bram_raddr <= 0;endelsebeginif(clken == 1'b1)beginif(bram_waddr < DATA_DEPTH)bram_waddr <= bram_waddr + 1'b1;elsebram_waddr <= 0;if(bram_raddr < DATA_DEPTH)bram_raddr <= bram_raddr + 1'b1;elsebram_raddr <= 0;endelsebeginbram_waddr <= bram_waddr;bram_raddr <= bram_raddr;endend
end//----------------------------------------------------------------------
wire [DATA_WIDTH-1:0] bram_wdata;
wire bram_wenb;
reg [DATA_WIDTH-1:0] bram_rdata;assign bram_wdata = din;
assign bram_wenb = clken;localparam ADDR_MSB = 2 ** ADDR_WIDTH - 1;
reg [DATA_WIDTH-1:0] r_ram[ADDR_MSB:0]; always @(posedge clk) beginif(bram_wenb) beginr_ram[bram_waddr] <= bram_wdata; end else beginend
end
always @(posedge clk) beginbram_rdata <= r_ram[bram_raddr];
endassign dout = bram_rdata;endmodule
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