Verilog刷题[hdlbits] ：Alwaysblock2

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题目：Alwaysblock2

For hardware synthesis, there are two types of always blocks that are relevant:
对于硬件综合，有两种相关的always块：

• Combinational: always @()
  组合型：always @()
• Clocked: always @(posedge clk)
  时钟型：always @(posedge clk)

Clocked always blocks create a blob of combinational logic just like combinational always blocks, but also creates a set of flip-flops (or “registers”) at the output of the blob of combinational logic. Instead of the outputs of the blob of logic being visible immediately, the outputs are visible only immediately after the next (posedge clk).
时钟型always块像组合型always块一样创建一个组合逻辑的blob，但还会在组合逻辑的输出处创建一组触发器（或“寄存器”）。与立即可见的逻辑blob的输出不同，输出只有在下一个（posedge clk）之后才能立即可见。

Blocking vs. Non-Blocking Assignment

阻塞赋值和非阻塞赋值

There are three types of assignments in Verilog:
Verilog中有三类赋值：

• Continuous assignments (assign x = y;). Can only be used when not
  inside a procedure (“always block”).
  连续赋值（assign x = y;）。只能在不处于过程（“always block”）内部时使用。
• Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
  过程阻塞赋值：（x = y;）。只能在过程内部使用。
• Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.
  过程非阻塞赋值：（x <= y;）。只能在过程内部使用。

In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments. A full understanding of why is not particularly useful for hardware design and requires a good understanding of how Verilog simulators keep track of events. Not following this rule results in extremely hard to find errors that are both non-deterministic and differ between simulation and synthesized hardware.
在组合型always块中使用阻塞赋值。在时钟型always块中使用非阻塞赋值。完全理解为什么这样做并不特别有助于硬件设计，需要对Verilog模拟器如何跟踪事件有深入的理解。如果不遵循这个规则，会导致非常难以找到的错误，这些错误既不是确定性的，也会在仿真和综合生成的硬件之间有所不同。

A bit of practice

一些实践

Build an XOR gate three ways, using an assign statement, a combinational always block, and a clocked always block. Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed.
用assign语句、组合型always块和时钟型always块三种方式构建一个XOR门。注意，时钟型always块产生的电路与其他两种不同：有一个触发器，所以输出被延迟了。

// synthesis verilog_input_version verilog_2001
module top_module(input clk,input a,input b,output wire out_assign,output reg out_always_comb,output reg out_always_ff   );//assign语句assign out_assign = a ^ b;//组合型always块always@(*)beginout_always_comb = a ^ b;end//时钟型always块always@(posedge clk)beginout_always_ff <= a ^ b;end
endmodule

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