Verilog刷题[hdlbits] ：Alwaysblock1

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题目：Alwaysblock1

Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit. Procedures (of which always blocks are one example) provide an alternative syntax for describing circuits.

由于数字电路由逻辑门和导线连接而成，任何电路都可以表示为模块和赋值语句的组合。然而，有时候这并不是描述电路最方便的方式。过程（其中总是块是一个示例）提供了一种用于描述电路的替代语法。

For synthesizing hardware, two types of always blocks are relevant:

对于硬件综合来说，有两种类型的总是块是相关的：

组合型：always @()
时钟型：always @(posedge clk)

Combinational always blocks are equivalent to assign statements, thus there is always a way to express a combinational circuit both ways. The choice between which to use is mainly an issue of which syntax is more convenient. The syntax for code inside a procedural block is different from code that is outside. Procedural blocks have a richer set of statements (e.g., if-then, case), cannot contain continuous assignments*, but also introduces many new non-intuitive ways of making errors. (*Procedural continuous assignments do exist, but are somewhat different from continuous assignments, and are not synthesizable.)

组合型总是块等价于赋值语句，因此总有一种方式可以同时表达组合电路。选择使用哪种方式主要是一个哪种语法更方便的问题。过程块内部的代码语法与外部的代码语法不同。过程块具有更丰富的语句集（例如if-then、case），不能包含连续赋值，但也引入了许多新的非直观的错误产生方式。（*虽然存在过程连续赋值，但与连续赋值有所不同，并且不可综合。）

For example, the assign and combinational always block describe the same circuit. Both create the same blob of combinational logic. Both will recompute the output whenever any of the inputs (right side) changes value.

例如，assign和combinational always块描述了相同的电路。它们都创建了相同的组合逻辑。无论输入（右侧）中的任何一个值发生变化，它们都会重新计算输出。

assign out1 = a & b | c ^ d;
always @() out2 = a & b | c ^ d;

For combinational always blocks, always use a sensitivity list of (). Explicitly listing out the signals is error-prone (if you miss one), and is ignored for hardware synthesis. If you explicitly specify the sensitivity list and miss a signal, the synthesized hardware will still behave as though (*) was specified, but the simulation will not and not match the hardware’s behaviour. (In SystemVerilog, use always_comb.)

对于组合型always块，始终使用（）的敏感列表。显式列出信号容易出错（如果遗漏一个信号），并且在硬件综合中会被忽略。如果您显式指定了敏感列表并遗漏了一个信号，综合后的硬件仍将按照（）指定的那样运行，但仿真将不会匹配硬件的行为。（在SystemVerilog中，使用always_comb。）

A note on wire vs. reg: The left-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg). These types (wire vs. reg) have nothing to do with what hardware is synthesized, and is just syntax left over from Verilog’s use as a hardware simulation language.

关于wire和reg的说明：assign语句的左侧必须是网络类型（例如wire），而过程赋值（在always块中）的左侧必须是变量类型（例如reg）。这些类型（wire和reg）与综合生成的硬件无关，只是Verilog作为硬件仿真语言遗留下来的语法。

// synthesis verilog_input_version verilog_2001
module top_module(input a, input b,output wire out_assign,output reg out_alwaysblock
);//assign语句assign out_assign = a & b;//always语句always@(*)beginout_alwaysblock = a & b;end
endmodule