[HDLBits] Exams/2014 q3bfsm

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Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.

Present state y[2:0]	Next state Y[2:0]		Output z
	x=0	x=1
000	000	001	0
001	001	100	0
010	010	001	0
011	001	010	1
100	011	100	1

module top_module (input clk,input reset,   // Synchronous resetinput x,output z
);reg [2:0] state,next;always@(*) begincase(state)3'b000:next<=x?001:000;3'b001:next<=x?100:001;3'b010:next<=x?001:010;3'b011:next<=x?010:001;3'b100:next<=x?100:011;endcaseendalways@(posedge clk) beginif(reset)state<=3'b000;elsestate<=next;endassign z=(state==3'b011||state==3'b100)?1:0;
endmodule

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