本文主要是介绍「HDLBits题解」Building Larger Circuits，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益
题目链接：Exams/review2015 count1k - HDLBits
module top_module (input clk,input reset,output [9:0] q
);always @(posedge clk) beginif (reset) q <= 0 ; else q <= q == 999 ? 0 : q + 1 ; endendmodule
题目链接：Exams/review2015 shiftcount - HDLBits
module top_module (input clk,input shift_ena,input count_ena,input data,output [3:0] q
);always @(posedge clk) beginif (shift_ena) q <= {q[2:0], data} ; else if (count_ena) q <= q - 1 ; else q <= q ; endendmodule
题目链接：Exams/review2015 fsmseq - HDLBits
module top_module (input clk,input reset, // Synchronous resetinput data,output start_shifting
);parameter idle = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4 ; reg [2:0] state, nstate ; always @(*) begincase (state)idle : nstate = data ? S1 : idle ; S1 : nstate = data ? S2 : idle ; S2 : nstate = data ? S2 : S3 ; S3 : nstate = data ? S4 : idle ; S4 : nstate = S4 ;endcaseendalways @(posedge clk) beginif (reset) state <= idle ; else state <= nstate ; endassign start_shifting = state == S4 ;endmodule
题目链接：Exams/review2015 fsmshift - HDLBits
module top_module (input clk,input reset, // Synchronous resetinput data,output start_shifting
);parameter idle = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4 ; reg [2:0] state, nstate ; always @(*) begincase (state)idle : nstate = data ? S1 : idle ; S1 : nstate = data ? S2 : idle ; S2 : nstate = data ? S2 : S3 ; S3 : nstate = data ? S4 : idle ; S4 : nstate = S4 ;endcaseendalways @(posedge clk) beginif (reset) state <= idle ; else state <= nstate ; endassign start_shifting = state == S4 ;endmodule题目链接：Exams/review2015 fsm - HDLBits
module top_module (input clk,input reset, // Synchronous resetinput data,output shift_ena,output counting,input done_counting,output done,input ack
);parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9 ; reg [3:0] nstate, state ; always @ (posedge clk) begin if (reset) state <= S ; else state <= nstate ; endalways @ (*) begin case (state) S : nstate = data ? S1 : S ;S1 : nstate = data ? S11 : S ; S11 : nstate = data ? S11 : S110 ; S110 : nstate = data ? B0 : S ; B0 : nstate = B1 ; B1 : nstate = B2 ; B2 : nstate = B3 ; B3 : nstate = Count ; Count : nstate = done_counting ? Wait : Count ; Wait : nstate = ack ? S : Wait ; endcaseendassign shift_ena = (state == B0 | state == B1 | state == B2 | state == B3) ; assign counting = (state == Count) ; assign done = (state == Wait) ;endmodule
题目链接：Exams/review2015 fancytimer - HDLBits
module top_module (input clk,input reset, // Synchronous resetinput data,input ack, output counting,output done,output [3:0] count
);parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9 ; reg [3:0] nstate, state ; reg [9:0] cnt ; always @ (posedge clk) begin if (reset) state <= S ; else state <= nstate ; endalways @ (*) begin case (state) S : nstate = data ? S1 : S ;S1 : nstate = data ? S11 : S ; S11 : nstate = data ? S11 : S110 ; S110 : nstate = data ? B0 : S ; B0 : nstate = B1 ; B1 : nstate = B2 ; B2 : nstate = B3 ; B3 : nstate = Count ; Count : nstate = (count == 0 & cnt == 999) ? Wait : Count ; Wait : nstate = ack ? S : Wait ; endcaseendalways @ (posedge clk) begin case (state) B0 : count[3] <= data ; B1 : count[2] <= data ; B2 : count[1] <= data ; B3 : count[0] <= data ; Count : begin if (count >= 0) if (cnt < 999) cnt <= cnt + 1 ; else begin count <= count - 1 ; cnt <= 0 ; endenddefault : cnt <= 0 ; endcaseendassign counting = (state == Count) ; assign done = (state == Wait) ; endmodule
题目链接：Exams/review2015 fsmonehot - HDLBits
module top_module(input d,input done_counting,input ack,input [9:0] state, // 10-bit one-hot current stateoutput B3_next,output S_next,output S1_next,output Count_next,output Wait_next,output done,output counting,output shift_ena
); //// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;assign B3_next = state[B2];assign S_next = (state[S] & (~d)) | (state[S1] & (~d)) | (state[S110] & (~d)) | (state[Wait] & ack);assign S1_next = state[S] & d;assign Count_next = state[B3] | (state[Count] & (~done_counting));assign Wait_next = (state[Count] & (done_counting)) | (state[Wait] & (~ack));assign done = state[Wait];assign counting = state[Count];assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3];endmodule这篇关于「HDLBits题解」Building Larger Circuits的文章就介绍到这儿，希望我们推荐的文章对编程师们有所帮助！
