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目录
前言
3.2.5 Finite State Machines
3.2.5.5 Simple state transitions 3(Fsm3comb)
3.2.5.6 Simple one-hot state transitions 3(Fsm3onehot)
3.2.5.7 Simple FSM 3 (asynchronous reset)(Fsm3)
3.2.5.8 Simple FSM 3 (synchronous reset)(Fsm3s)
3.2.5.9 Design a Moore FSM (Exams/ece241 2013 q4)
结语
HDLbits网站链接
前言
今天接着更新状态机部分的习题答案。
3.2.5 Finite State Machines
3.2.5.5 Simple state transitions 3(Fsm3comb)
module top_module(input in,input [1:0] state,output [1:0] next_state,output out); //parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;always@(*)begincase(state)A:beginnext_state = in ? B : A;endB:beginnext_state = in ? B : C;endC:beginnext_state = in ? D : A;endD:beginnext_state = in ? B : C;end
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