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clk_a 周期为10ns
clk_b 周期为34ns
代码:
module pulse(input clk_a,input clk_b,input signal_a,output reg signal_b);reg [4:0] signal_a_widen_maker = 0;reg signal_a_widen;always @(posedge clk_a)if(signal_a) signal_a_widen_maker [0]<= 1;else beginsignal_a_widen_maker = signal_a_widen_maker<<1;if(signal_a_widen_maker[4] == 1)signal_a_widen_maker<=0;end always @(posedge clk_a)if((|signal_a_widen_maker)||signal_a)signal_a_widen <= 1;else signal_a_widen <= 0;reg [1:0] signal_b_reg;always @(posedge clk_b) begin signal_b_reg[0] <= signal_a_widen;signal_b_reg[1] <= signal_b_reg[0];endalways @(posedge clk_b) if(signal_b_reg == 2'b01)signal_b <= 1;else signal_b <= 0;endmodule testb
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