FPGA的俩位数码管动态扫描

本文主要是介绍FPGA的俩位数码管动态扫描，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！

也写了个简单的顶层，和底层。

module key2led(
clk,
rstn,
key1,
led,
led2,
dig,
sel
);

input clk, rstn;
input key1;
output led,led2;
output [7:0] dig;
output [1:0] sel;
led u1(
.key1(key1),
.led(led),
.clk(clk),
.led2(led2),
.dig(dig),
.sel(sel)
);
endmodule

module led (
key1,
led,
clk,
led2,
dig,
sel
);

input key1,clk;
output led,led2;
output reg [7:0]dig;
output reg [1:0]sel;

reg [3:0] count;
reg [3:0] count_xianshi;
reg [3:0] count_shiwei;
reg led;
reg led2;
reg [31:0] counter;

parameter xianshi_time= 60000 ;

reg [32:0] sel_time ;

always @( posedge clk ) begin
   sel_time<=sel_time+1'b1;
if(sel_time<xianshi_time)begin
sel<=2'b01;
  count_xianshi<=count_shiwei;end
else if (sel_time>xianshi_time&&sel_time<xianshi_time*2)begin
sel<=2'b10;
  count_xianshi<=count;end
else if (sel_time==xianshi_time*3)
sel_time<=0;
end

always @( posedge clk ) begin
counter<=counter+1'b1;
if(counter==100000) begin
led2<=1'b1;
end
if(counter==200000) begin
led2<=1'b0;
end
if(counter==4000000) begin
count<=count+1'b1;
end
if(counter==50000000) begin
counter<=32'b0;
end
if(count>9) begin
count_shiwei<=count_shiwei+1'b1;
count<=0;
end
if(count_shiwei>9) begin
count_shiwei<=count_shiwei;
end
end
always @( posedge clk) begin
if (key1==1'b1)
led<=1'b1;

else begin
led<=1'b0;
end
end

always @( posedge clk) begin
case (count_xianshi)
0: begin
  dig[0]<=1'b0;//0是数码管亮显示0
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b0;
    dig[5]<=1'b0;
   dig[6]<=1'b1;
  dig[7]<=1'b1;
  end
1: begin
  dig[0]<=1'b1;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b1;
   dig[4]<=1'b1;
    dig[5]<=1'b1;
   dig[6]<=1'b1;
  dig[7]<=1'b1;
  end
2: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b1;
   dig[3]<=1'b0;
   dig[4]<=1'b0;
    dig[5]<=1'b1;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
3: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b1;
    dig[5]<=1'b1;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
4: begin
  dig[0]<=1'b1;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b1;
   dig[4]<=1'b1;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
5: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b1;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b1;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
6: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b1;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b0;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
7: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b1;
   dig[4]<=1'b1;
    dig[5]<=1'b1;
   dig[6]<=1'b1;
  dig[7]<=1'b1;
  end
8: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b0;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
9: begin
  dig[0]<=1'b0;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b0;
   dig[4]<=1'b1;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
  end
default: begin
  dig[0]<=1'b1;//0是数码管亮显示 1
  dig[1]<=1'b0;
      dig[2]<=1'b0;
   dig[3]<=1'b1;
   dig[4]<=1'b1;
    dig[5]<=1'b0;
   dig[6]<=1'b0;
  dig[7]<=1'b1;
end
endcase
end

endmodule