有符号数间比较,及有符号数与常数比较 Verilog代码示例 module data_cmp#(parameter DW = 16)(input signed [DW-1:0] a1,input signed [DW-1:0] b1,input signed [DW/4-1:0] a2,input signed [DW/4-1:0] b2);// constant
有符号数间比较,及有符号数与常数比较 Verilog代码示例 module data_cmp#(parameter DW = 16)(input signed [DW-1:0] a1,input signed [DW-1:0] b1,input signed [DW/4-1:0] a2,input signed [DW/4-1:0] b2);// constant