IP核 tb_com module tb_com();reg ad9361_l_clk,rst; initial beginad9361_l_clk=0;forever #4.545 ad9361_l_clk=~ad9361_l_clk;endinitial beginrst=1;#9.09 rst=0;endwire [63 : 0] m_fll_phase_shift_d