Cadence招聘IP研发工程师

1. Principal/Lead/Senior Physical Design Engineer

Position Description:

 Focus on high speed digital DDR and HBM IP physical implementation

 Have good physical design experiences in the digital implementation domain including Floorplan, P&R, Physical verification, DFM.

 Have a solid background in circuits, electronics & physics & should be very willing to learn new technology for advance node and design methodology

 Skilled in scripting language, such as Perl, C shell, Make file

 Feeling responsible for technical delivery, good team played, design quality/schedule focus

Position Requirements:

 Essential Qualifications: Have MS degree with 2 ~4+ years of applicable experience, MS degree with 4 ~ 6+years of applicable experience in electrical engineering, microelectronics.

 Essential that the individual demonstrates strong communication skill

 Requires good communication skills in English.

2. Lead Product Engineer- DDR PHY

Position Description:

 Cadence is looking for an individual to work in an established memory controller design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing technical support to customers, however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities.

Provide technical support to customers for integration of IP into ASICs including:

 Debugging of customers’ simulation or silicon issues.

 Reviewing of customers’ integration of our IP.

 Reviewing static timing reports to assist with customers’ timing closure.

 Answering technical questions about IP operation.

 Train field engineers in IP operation.

 Interface with the R&D Team to bridge product improvements and resolve customer issues.

Position Requirements:

 Excellent oral and written communication.

 BS + 5 years of prior work-experience or MS + 2 years of prior work-experience

 All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT

 Back-end skills – place & route, physical verification, timing closure

 Time management skills sufficient to balance multiple high-priority projects.

 Willingness to learn new skills and perform tasks that often go outside area of current expertise.

Additional Desirable Qualifications:

 Experience with Static Timing scripts and report analysis

 Familiarity with DDR memory operation, system applications, AXI, OCP, AHB

 Familiarity with Frame maker

 Scripting – in Perl, TCL, etc.

3. Senior Program Manager

Position Description:

 We are looking for a Senior Program Manager who will be responsible for the overall coordination of Key Customer Engagements and R&D Development Projects within the Design IP Group. The candidate must have experience in IP and/or SoC Design and a history in successfully program managing complex IP/SoC Programs with end customers. A PMP Certification or equivalent is desirable.

Main Job Tasks and Responsibilities

 lead the planning and track the implementation of project

 facilitate the definition of project scope, goals and deliverables

 define project tasks and resource requirements

 develop full scale project plans

 manage/track project resource allocation

 plan and schedule project timelines

 track project deliverables using appropriate tools

 provide direction and support to project team

 support quality assurance

 constantly monitor and report on progress of the project to all stakeholders

 present reports defining project progress, problems and solutions

 implement and manage project changes and interventions to achieve project outputs

 manage customer engagement – project and relationship management

 collaborate with Sales, Marketing, Finance and Engineering to assure effective and efficient project execution

Position Requirements:

Education and Experience

 knowledge of both theoretical and practical aspects of project management

 knowledge of project management techniques and tools

 direct work experience in project management capacity

 proven experience in people management

 proven experience in strategic planning

 proven experience in risk management

 proven experience in change management

 proficient in project management software

 min 7+ years verifiable successes managing SoC/IP deliverables

 BSEE at a min. MSEE & MBA preferred

Key competencies

 critical thinking and problem solving skills

 planning and organizing

 decision-making

 communication skills

 influencing and leading

 team work

 conflict management

 adaptability

4. Principal Design Engineer

Position Description:

 Cadence/Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible for verification of advanced DSP cores and their instruction set architectures and hardware implementations. You will implement architectural simulation test benches in C/C++/RTL, write C/assembly language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test plans, debugging failures and analyzing coverage information. You will work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.

Position Requirements:

 Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processor architecture concepts

 Good knowledge of C (C++ will be a plus)

 Working knowledge of Verilog and popular EDA simulators and testbench methodologies

 Knowledge of scripting languages such as Makefile/Perl is desired

 Knowledge of assembly programming and programming in a high level language such as C

 Good English communication skills – both written and verbal

 Strong problem solving skills along with an ability to work independently and in cooperation with global teams

 MS degree in EE/CS with 3 to 5 years industry experience required.