6、zedboard之纯PL流水灯实验

本文主要是介绍6、zedboard之纯PL流水灯实验，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！

基本思想：想着最近在复习一下FPGA开发，准备接个大项目
熟悉工具vivado2021_1，许可2017-2021
芯片厂商

一、首先选择芯片类型

二、约束文件
led_demo.xdc

set_property PACKAGE_PIN K17 [get_ports clk]
set_property PACKAGE_PIN E17 [get_ports rst_n]
set_property PACKAGE_PIN M15 [get_ports {led[0]}]
set_property PACKAGE_PIN G14 [get_ports {led[1]}]
set_property PACKAGE_PIN M17 [get_ports {led[2]}]
set_property PACKAGE_PIN G15 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]

三、源代码
led_demo.v

`timescale 1ns / 1ps
module led_demo(input  clk ,
input  rst_n ,output reg [3:0]led );//50MHZ 1/50MHZ=0.02us  1s=1000000/0.02us=1000 000 00/2=50 000 000reg [28:0] cnt ;
always@(posedge clk or negedge rst_n)if(!rst_n)cnt <= 0 ;
else if(cnt==28'd50_000_000)cnt <= 0 ;
elsecnt <= cnt+1'b1 ;reg [3:0] shifter;
always@(posedge clk or negedge rst_n)
if(!rst_n)shifter<=4'b0111;
else if(cnt==28'd50_000_000)shifter<={shifter[2:0],shifter[3]};always@(posedge clk or negedge rst_n)
if(!rst_n)led <=4'b1111 ;
else if(cnt==28'd50_000_000)led <= shifter ;endmodule

四、测试结果

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