vivado报错 遇到困难不要怕

2023.8.21

[Designutils 20-1733] GTHE2 is not supported for the device xc7k420tffg1156-2

事情经过：在给工程换板子时候，ip_update日志显示-Upgrade has removed port 'gt0_qpll_lock_in'；

gt0_qpll_lock_in这个信号总是被优化掉了。

后续是把srio的IP核解锁跟新。

2023.8.21

[DRC REQP-1960] GTXE2_valid_QPLL_input_clock_driver: GTXE2_CHANNEL cell u_sata_platform/gtwizard_support_i/gtwizard_init_i/inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i: The u_sata_platform/gtwizard_support_i/gtwizard_init_i/inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i/QPLLCLK input clock pin may only be driven by a GTXE2_COMMON or another GTXE2_CHANNEL, instead of u_sata_platform/gtwizard_support_i/common0_i/gthe2_common_i

后续。。。换成srio例程的common模块就不报错了

2023.8.23

[Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

事情经过：还是因为换了板子，软件有一个复位的操作，复位后一直报找不到ila了；

后续。。。这个问题整整折磨了三天多，从修改程序到重新建程序，最后使用原本程序才发现是设备重启后会自动烧录固有bit，ila都不匹配怎么能看ila呢。研究了那么久的代码竟不如破罐子破摔。

2023.8.28

ERROR: [Labtools 27-3165] End of startup status: LOW

线没接好。

2023.9.25

[DRC REQP-43] must_use_ref_clock: GTHE2_CHANNEL cell siro0_share_111_inst/chnl_loop[0].design_1_wrapper_isnt/design_1_i/srio_gen2_0/inst/srio_gt_wrapper_inst/inst/gtwizard_0_i/gt0_gtwizard_0_i/gthe2_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set CPLLREFCLKSEL[2:0] appropriately) or GTHE2_COMMON clock input (QPLLCLK) must be used.

实验目的：将srio模块添加进block_design

原因：common模块的信号没有正确连接srio模块的信号

2023.9.25

[DRC REQP-1619] IBUFDS_GTE2_driven_by_IBUF: IBUFDS_GTE2 siro0_share_111_inst/srio_clk_inst/u_refclk_ibufds pins I and IB should be driven by IBUFs.

实验目的：将srio模块添加进block_design

原因：srio的rx，tx接口没有正确连接会出现管脚不能自动绑定和以上报错的情况。

2023.10.9

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk] >

解决方法：添加xdc代码

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets diff_clock_rtl_0_clk_p_clk_p]

2023.10.9 

【SDK串口助手打印数据和设置的数据不对应】

选择【run configrations】-【reset entire system】

2023.10.16

【SDK运行报错】
问题：sdk查看srio地址一运行地址就打印一大片问号

[1]Error while launching program:
Memory write error at 0x80000000. MicroBlaze instruction insert overrun

[2]cannot stop microblze.Stalled on instruction fetch

 首先查看sdk的lscript.ld文件，查看Memory Region选的是哪个内存

再次检查代码地址是否指令地址和数据地址冲突，注意选择的数据地址要比DDR的首地址要大，且代码中不能超过比DDR最高地址要大的地址。

2023.10.18

[Timing 38-469] The REFCLK pin of IDELAYCTRL design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.

解决方法：mig选项卡 referrence clock勾选no buffer，将引出的clk 连接到clk ip输出的时钟管脚。

2023.10.18

[Runs 36-527] DCP does not exist: c:/Users/zh/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6536-DESKTOP-TRVG50K/coregen/design_1_mig_7series_0_0/design_1_mig_7series_0_0.dcp

解决方法：选下面这两个