uboot1.1.6移植

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TX2440_config : unconfig

@$(MKCONFIG) $(@:_config=) armarm920tTX2440NULL s3c24x0

arm：CPU的构架(ARCH)

arm920t:CPU类型，对应于cpu/arm920t子目录。

TX2440开发板的型号(BOARD),对应于 board/TX2440 目录。

NULL:开发者/经销商(vender)。

s3c24x0：片上系统(SOC)。

指定交叉编译器(128行)，也可以写绝对路径

ifeq ($(ARCH),arm)
CROSS_COMPILE = arm-linux-

如果出现这个就表明已经配置成功。

---------------------------------------------------------------------------------------------------------初始化内存---------------------------------------------------------------------------------------------------------------

修改SDRAM(存储控制器)配置，调用了这个文件来初始化内存

-------------------------------------------------------------------------------------------------------------设置时钟----------------------------------------------------------------------------------------------------------

设置TX2440的时钟

/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/

#include <common.h>
#include <s3c2410.h>

DECLARE_GLOBAL_DATA_PTR;

#define FCLK_SPEED 1

#if FCLK_SPEED==0       /* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
#elif FCLK_SPEED==1     /* Fout = 202.8MHz */
#define M_MDIV 0xA1
#define M_PDIV 0x3
#define M_SDIV 0x1
#endif

#define USB_CLOCK 1

#if USB_CLOCK==0
#define U_M_MDIV    0xA1
#define U_M_PDIV    0x3
#define U_M_SDIV    0x1
#elif USB_CLOCK==1
#define U_M_MDIV    0x48
#define U_M_PDIV    0x3
#define U_M_SDIV    0x2
#endif

static inline void delay (unsigned long loops)
{
    __asm__ volatile ("1:\n"
      "subs %0, %1, #1\n"
      "bne 1b":"=r" (loops):"0" (loops));
}

/*
* Miscellaneous platform dependent initialisations
*/

/* S3C2440: Mpll,Upll = (2*m * Fin) / (p * 2^s)
* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
*/
#define S3C2440_MPLL_400MHZ ((0x7f<<12)|(0x02<<4)|(0x01))
#define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02))
#define S3C2440_CLKDIV 0x05 /* FCLK:HCLK:PCLK = 1:4:8 */
/* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s)
* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
*/
#define S3C2410_MPLL_200MHZ ((0x5c<<12)|(0x04<<4)|(0x00))
#define S3C2410_UPLL_48MHZ ((0x28<<12)|(0x01<<4)|(0x02))
#define S3C2410_CLKDIV 0x03 /* FCLK:HCLK:PCLK = 1:2:4 */
int board_init (void)
{

    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
    /* set up the I/O ports */
    gpio->GPACON = 0x007FFFFF;
    gpio->GPBCON = 0x00044555;
    gpio->GPBUP = 0x000007FF;
    gpio->GPCCON = 0xAAAAAAAA;
    gpio->GPCUP = 0x0000FFFF;
    gpio->GPDCON = 0xAAAAAAAA;
    gpio->GPDUP = 0x0000FFFF;
    gpio->GPECON = 0xAAAAAAAA;
    gpio->GPEUP = 0x0000FFFF;
    gpio->GPFCON = 0x000055AA;
    gpio->GPFUP = 0x000000FF;
    gpio->GPGCON = 0xFF95FFBA;
    gpio->GPGUP = 0x0000FFFF;
    gpio->GPHCON = 0x002AFAAA;
    gpio->GPHUP = 0x000007FF;

    /*support both of S3C2410 and S3C2440*/
    if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))
    {
        /*FCLK:HCLK:PCLK = 1:2:4*/
        clk_power->CLKDIVN = S3C2410_CLKDIV;

        /* change to asynchronous bus mod */
        __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */
                "orr r1, r1, #0xc0000000\n" /* Asynchronous */
                "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */
                :::"r1"
                );

        /* to reduce PLL lock time, adjust the LOCKTIME register */
        clk_power->LOCKTIME = 0xFFFFFF;

        /* configure MPLL */
        clk_power->MPLLCON = S3C2410_MPLL_200MHZ;

        /* some delay between MPLL and UPLL */
        delay (4000);

        /* configure UPLL */
        clk_power->UPLLCON = S3C2410_UPLL_48MHZ;
        /* some delay between MPLL and UPLL */
        delay (8000);

        /* arch number of SMDK2410-Board */
        gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
    }
    else
    {
        /* FCLK:HCLK:PCLK = 1:4:8 */
        clk_power->CLKDIVN = S3C2440_CLKDIV;

        /* change to asynchronous bus mod */
        __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */
                "orr r1, r1, #0xc0000000\n" /* Asynchronous */
                "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */
                :::"r1"
                );

        /* to reduce PLL lock time, adjust the LOCKTIME register */
        clk_power->LOCKTIME = 0xFFFFFF;

        /* configure MPLL */
        clk_power->MPLLCON = S3C2440_MPLL_400MHZ;

        /* some delay between MPLL and UPLL */
        delay (4000);

        /* configure UPLL */
        clk_power->UPLLCON = S3C2440_UPLL_48MHZ;

        /* some delay between MPLL and UPLL */
        delay (8000);

        /* arch number of SMDK2440-Board */
        gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
    }

    /* adress of boot parameters */
    gd->bd->bi_boot_params = 0x30000100;
    icache_enable();
    dcache_enable();
    return 0;
}

int dram_init (void)
{
    gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
    gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

    return 0;
}

在程序的开头增加这一行

在 static ulong get_PLLCLK(int pllreg)后面增加这几句

    if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
         return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
    else
         return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s)); /* S3C2440 */

修改get_HCLK 和 get_PCLK

/*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/

/* This code should work for both the S3C2400 and the S3C2410
* as they seem to have the same PLL and clock machinery inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/

#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)

#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif

#define MPLL 0
#define UPLL 1
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */

static ulong get_PLLCLK(int pllreg)
{
    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    ulong r, m, p, s;

    if (pllreg == MPLL)
        r = clk_power->MPLLCON;

    else if (pllreg == UPLL)
        r = clk_power->UPLLCON;

    else
      hang();

    m = ((r & 0xFF000) >> 12) + 8;
    p = ((r & 0x003F0) >> 4) + 2;
    s = r & 0x3;

    /* support both of S3C2410 and S3C2440 */
    if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
         return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
    else
         return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s)); /* S3C2440 */

}

/* return FCLK frequency */
ulong get_FCLK(void)
{
    return(get_PLLCLK(MPLL));
}

/* return HCLK frequency */

/* for s3c2440 */
#define S3C2440_CLKDIVN_PDIVN (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
#define S3C2440_CLKDIVN_UCLK (1<<3)
#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
#define S3C2440_CAMDIVN_DVSEN (1<<12)

/* return HCLK frequency */
ulong get_HCLK(void)
{
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        unsigned long clkdiv;
        unsigned long camdiv;

        int hdiv = 1;

        /* support both of S3C2410 and S3C2440 */
        if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
               return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
        else
        {
            clkdiv = clk_power->CLKDIVN;
            camdiv = clk_power->CAMDIVN;

            /* work out clock scalings */
            switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
            {
                    case S3C2440_CLKDIVN_HDIVN_1:
                    hdiv = 1;
                    break;

                    case S3C2440_CLKDIVN_HDIVN_2:
                    hdiv = 2;
                    break;

                    case S3C2440_CLKDIVN_HDIVN_4_8:
                    hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
                    break;

                    case S3C2440_CLKDIVN_HDIVN_3_6:
                    hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
                    break;

            }

                return get_FCLK() / hdiv;
        }

}

/* return PCLK frequency */
ulong get_PCLK(void)
{
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        unsigned long clkdiv;
        unsigned long camdiv;
        int hdiv = 1;

        /* support both of S3C2410 and S3C2440 */
        if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
                return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
        else
        {
                clkdiv = clk_power->CLKDIVN;
                camdiv = clk_power->CAMDIVN;
                /* work out clock scalings */
                switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK)
                {
                        case S3C2440_CLKDIVN_HDIVN_1:
                        hdiv = 1;
                        break;

                        case S3C2440_CLKDIVN_HDIVN_2:
                        hdiv = 2;
                        break;

                        case S3C2440_CLKDIVN_HDIVN_4_8:
                        hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
                        break;

                        case S3C2440_CLKDIVN_HDIVN_3_6:
                        hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
                        break;

                }

                return get_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);

        }

}

/* return UCLK frequency */
ulong get_UCLK(void)
{
    return(get_PLLCLK(UPLL));
}

#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */