VIVADO自定义 IP封装

本文主要是介绍VIVADO自定义 IP封装，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
简介

本章节主要针对VIVAO 2020.2版本做IP自定义封装，其中涉及到IP寄存器读写配置，自定义接口封装等介绍。
IP封装

IP标准自定义步骤一般有创建工程，封装IP，自定义内容，添加自定义库这4个步骤，下面就每个步骤详细介绍。
创建工程

以寄存器读写IP为例子，自定义封装一个IP模块，首先创建工程，如下图所示：
创建的工程名为cmd_reg。
选择RTL工程。
本次FPGA芯片选用XC7A35TFFG484-2芯片信号。
以上工程创建完毕。
封装IP

工程创建完毕后便可做程序编写了，如果是自定义功能模块可编写代码，然后封装，本工程主要是基于上位机对FPGA寄存器读写的功能模块，所以直接调用reg模块封装，如下图所示：
创建封装后自定义IP有添加AXI4和不添加AXI4总线选择，本次选择添加AXI4总线，如下图所示：
图中1是直接封装自定义IP库，2是添加AXI4总线封装。
图中编号代表意思
1、IP名称；
2、IP版本号；
3、IP展现的名字，这个展现的名字根据1、2生成；
4、IP描述；
5、IP生成所在位置。
上图解析如下：
1、AXI总线命名；
2、AXI总线类型，我们只是寄存器读写，选择lite；
3、AXI总线模式，即主模式和从模式，一般FPGA作为从端，PS或者microblaze作为主，这里选择slave；
4、寄存器数据位宽，32位；
5、寄存器个数，根据需要选择。
填写完毕点击NEXT。
选择编辑库，点击FINISH。
自定义内容

如下图所示：
图中1和2是AXI_LITE的基本代码，3是自定义详细信息。
本设计针对寄存器模块主要添加如下接口：
更改后的代码可以通过读写使能的方式直接操作寄存器的读写，可以理解为将繁琐的AXI总线映射成简单的读写使能方式操作。
更改代码如下：

`timescale 1 ns / 1 psmodule cmd_reg_v1_0_S00_AXI #(// Users to add parameters here// User parameters ends// Do not modify the parameters beyond this line// Width of S_AXI data busparameter integer C_S_AXI_DATA_WIDTH	= 32,// Width of S_AXI address busparameter integer C_S_AXI_ADDR_WIDTH	= 8)(// Users to add ports hereoutput wire[5:0]  reg_wr_addr,output wire slv_reg_wren,output wire[31:0] reg_wr_data,output wire[5:0]  reg_rd_addr,output wire reg_rd_en,input wire[31:0] reg_rd_data,// User ports ends// Do not modify the ports beyond this line// Global Clock Signalinput wire  S_AXI_ACLK,// Global Reset Signal. This Signal is Active LOWinput wire  S_AXI_ARESETN,// Write address (issued by master, acceped by Slave)input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,// Write channel Protection type. This signal indicates the// privilege and security level of the transaction, and whether// the transaction is a data access or an instruction access.input wire [2 : 0] S_AXI_AWPROT,// Write address valid. This signal indicates that the master signaling// valid write address and control information.input wire  S_AXI_AWVALID,// Write address ready. This signal indicates that the slave is ready// to accept an address and associated control signals.output wire  S_AXI_AWREADY,// Write data (issued by master, acceped by Slave) input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,// Write strobes. This signal indicates which byte lanes hold// valid data. There is one write strobe bit for each eight// bits of the write data bus.    input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,// Write valid. This signal indicates that valid write// data and strobes are available.input wire  S_AXI_WVALID,// Write ready. This signal indicates that the slave// can accept the write data.output wire  S_AXI_WREADY,// Write response. This signal indicates the status// of the write transaction.output wire [1 : 0] S_AXI_BRESP,// Write response valid. This signal indicates that the channel// is signaling a valid write response.output wire  S_AXI_BVALID,// Response ready. This signal indicates that the master// can accept a write response.input wire  S_AXI_BREADY,// Read address (issued by master, acceped by Slave)input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,// Protection type. This signal indicates the privilege// and security level of the transaction, and whether the// transaction is a data access or an instruction access.input wire [2 : 0] S_AXI_ARPROT,// Read address valid. This signal indicates that the channel// is signaling valid read address and control information.input wire  S_AXI_ARVALID,// Read address ready. This signal indicates that the slave is// ready to accept an address and associated control signals.output wire  S_AXI_ARREADY,// Read data (issued by slave)output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,// Read response. This signal indicates the status of the// read transfer.output wire [1 : 0] S_AXI_RRESP,// Read valid. This signal indicates that the channel is// signaling the required read data.output wire  S_AXI_RVALID,// Read ready. This signal indicates that the master can// accept the read data and response information.input wire  S_AXI_RREADY);// AXI4LITE signalsreg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;reg  	axi_awready;reg  	axi_wready;reg [1 : 0] 	axi_bresp;reg  	axi_bvalid;reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;reg  	axi_arready;reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;reg [1 : 0] 	axi_rresp;reg  	axi_rvalid;// Example-specific design signals// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH// ADDR_LSB is used for addressing 32/64 bit registers/memories// ADDR_LSB = 2 for 32 bits (n downto 2)// ADDR_LSB = 3 for 64 bits (n downto 3)localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;localparam integer OPT_MEM_ADDR_BITS = 5;//----------------------------------------------//-- Signals for user logic register space example//------------------------------------------------//-- Number of Slave Registers 64reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg10;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg11;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg12;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg13;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg14;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg15;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg16;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg17;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg18;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg19;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg20;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg21;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg22;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg23;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg24;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg25;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg26;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg27;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg28;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg29;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg30;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg31;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg32;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg33;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg34;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg35;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg36;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg37;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg38;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg39;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg40;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg41;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg42;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg43;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg44;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg45;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg46;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg47;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg48;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg49;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg50;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg51;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg52;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg53;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg54;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg55;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg56;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg57;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg58;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg59;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg60;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg61;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg62;reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg63;wire	 slv_reg_rden;//wire	 slv_reg_wren;reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;integer	 byte_index;reg	 aw_en;// I/O Connections assignmentsassign S_AXI_AWREADY	= axi_awready;assign S_AXI_WREADY	= axi_wready;assign S_AXI_BRESP	= axi_bresp;assign S_AXI_BVALID	= axi_bvalid;assign S_AXI_ARREADY	= axi_arready;assign S_AXI_RDATA	= axi_rdata;assign S_AXI_RRESP	= axi_rresp;assign S_AXI_RVALID	= axi_rvalid;// Implement axi_awready generation// axi_awready is asserted for one S_AXI_ACLK clock cycle when both// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is// de-asserted when reset is low.always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_awready <= 1'b0;aw_en <= 1'b1;end elsebegin    if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)begin// slave is ready to accept write address when // there is a valid write address and write data// on the write address and data bus. This design // expects no outstanding transactions. axi_awready <= 1'b1;aw_en <= 1'b0;endelse if (S_AXI_BREADY && axi_bvalid)beginaw_en <= 1'b1;axi_awready <= 1'b0;endelse           beginaxi_awready <= 1'b0;endend end       // Implement axi_awaddr latching// This process is used to latch the address when both // S_AXI_AWVALID and S_AXI_WVALID are valid. always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_awaddr <= 0;end elsebegin    if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)begin// Write Address latching axi_awaddr <= S_AXI_AWADDR;endend end       // Implement axi_wready generation// axi_wready is asserted for one S_AXI_ACLK clock cycle when both// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is // de-asserted when reset is low. always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_wready <= 1'b0;end elsebegin    if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )begin// slave is ready to accept write data when // there is a valid write address and write data// on the write address and data bus. This design // expects no outstanding transactions. axi_wready <= 1'b1;endelsebeginaxi_wready <= 1'b0;endend end       // Implement memory mapped register select and write logic generation// The write data is accepted and written to memory mapped registers when// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to// select byte enables of slave registers while writing.// These registers are cleared when reset (active low) is applied.// Slave register write enable is asserted when valid address and data are available// and the slave is ready to accept the write address and write data.assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginslv_reg0 <= 0;slv_reg1 <= 0;slv_reg2 <= 0;slv_reg3 <= 0;slv_reg4 <= 0;slv_reg5 <= 0;slv_reg6 <= 0;slv_reg7 <= 0;slv_reg8 <= 0;slv_reg9 <= 0;slv_reg10 <= 0;slv_reg11 <= 0;slv_reg12 <= 0;slv_reg13 <= 0;slv_reg14 <= 0;slv_reg15 <= 0;slv_reg16 <= 0;slv_reg17 <= 0;slv_reg18 <= 0;slv_reg19 <= 0;slv_reg20 <= 0;slv_reg21 <= 0;slv_reg22 <= 0;slv_reg23 <= 0;slv_reg24 <= 0;slv_reg25 <= 0;slv_reg26 <= 0;slv_reg27 <= 0;slv_reg28 <= 0;slv_reg29 <= 0;slv_reg30 <= 0;slv_reg31 <= 0;slv_reg32 <= 0;slv_reg33 <= 0;slv_reg34 <= 0;slv_reg35 <= 0;slv_reg36 <= 0;slv_reg37 <= 0;slv_reg38 <= 0;slv_reg39 <= 0;slv_reg40 <= 0;slv_reg41 <= 0;slv_reg42 <= 0;slv_reg43 <= 0;slv_reg44 <= 0;slv_reg45 <= 0;slv_reg46 <= 0;slv_reg47 <= 0;slv_reg48 <= 0;slv_reg49 <= 0;slv_reg50 <= 0;slv_reg51 <= 0;slv_reg52 <= 0;slv_reg53 <= 0;slv_reg54 <= 0;slv_reg55 <= 0;slv_reg56 <= 0;slv_reg57 <= 0;slv_reg58 <= 0;slv_reg59 <= 0;slv_reg60 <= 0;slv_reg61 <= 0;slv_reg62 <= 0;slv_reg63 <= 0;end else beginif (slv_reg_wren)begincase ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )6'h00:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 0slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h01:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 1slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h02:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 2slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h03:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 3slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h04:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 4slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h05:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 5slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h06:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 6slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h07:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 7slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h08:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 8slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h09:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 9slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0A:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 10slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0B:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 11slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0C:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 12slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0D:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 13slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0E:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 14slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h0F:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 15slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h10:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 16slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h11:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 17slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h12:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 18slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h13:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 19slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h14:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 20slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h15:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 21slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h16:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 22slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h17:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 23slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h18:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 24slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h19:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 25slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1A:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 26slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1B:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 27slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1C:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 28slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1D:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 29slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1E:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 30slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h1F:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 31slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h20:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 32slv_reg32[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h21:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 33slv_reg33[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h22:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 34slv_reg34[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h23:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 35slv_reg35[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h24:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 36slv_reg36[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h25:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 37slv_reg37[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h26:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 38slv_reg38[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h27:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 39slv_reg39[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h28:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 40slv_reg40[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h29:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 41slv_reg41[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2A:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 42slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2B:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 43slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2C:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 44slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2D:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 45slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2E:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 46slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h2F:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 47slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h30:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 48slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h31:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 49slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h32:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 50slv_reg50[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h33:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 51slv_reg51[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h34:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 52slv_reg52[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h35:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 53slv_reg53[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h36:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 54slv_reg54[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h37:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 55slv_reg55[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h38:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 56slv_reg56[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h39:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 57slv_reg57[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3A:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 58slv_reg58[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3B:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 59slv_reg59[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3C:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 60slv_reg60[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3D:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 61slv_reg61[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3E:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 62slv_reg62[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  6'h3F:for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )if ( S_AXI_WSTRB[byte_index] == 1 ) begin// Respective byte enables are asserted as per write strobes // Slave register 63slv_reg63[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];end  default : beginslv_reg0 <= slv_reg0;slv_reg1 <= slv_reg1;slv_reg2 <= slv_reg2;slv_reg3 <= slv_reg3;slv_reg4 <= slv_reg4;slv_reg5 <= slv_reg5;slv_reg6 <= slv_reg6;slv_reg7 <= slv_reg7;slv_reg8 <= slv_reg8;slv_reg9 <= slv_reg9;slv_reg10 <= slv_reg10;slv_reg11 <= slv_reg11;slv_reg12 <= slv_reg12;slv_reg13 <= slv_reg13;slv_reg14 <= slv_reg14;slv_reg15 <= slv_reg15;slv_reg16 <= slv_reg16;slv_reg17 <= slv_reg17;slv_reg18 <= slv_reg18;slv_reg19 <= slv_reg19;slv_reg20 <= slv_reg20;slv_reg21 <= slv_reg21;slv_reg22 <= slv_reg22;slv_reg23 <= slv_reg23;slv_reg24 <= slv_reg24;slv_reg25 <= slv_reg25;slv_reg26 <= slv_reg26;slv_reg27 <= slv_reg27;slv_reg28 <= slv_reg28;slv_reg29 <= slv_reg29;slv_reg30 <= slv_reg30;slv_reg31 <= slv_reg31;slv_reg32 <= slv_reg32;slv_reg33 <= slv_reg33;slv_reg34 <= slv_reg34;slv_reg35 <= slv_reg35;slv_reg36 <= slv_reg36;slv_reg37 <= slv_reg37;slv_reg38 <= slv_reg38;slv_reg39 <= slv_reg39;slv_reg40 <= slv_reg40;slv_reg41 <= slv_reg41;slv_reg42 <= slv_reg42;slv_reg43 <= slv_reg43;slv_reg44 <= slv_reg44;slv_reg45 <= slv_reg45;slv_reg46 <= slv_reg46;slv_reg47 <= slv_reg47;slv_reg48 <= slv_reg48;slv_reg49 <= slv_reg49;slv_reg50 <= slv_reg50;slv_reg51 <= slv_reg51;slv_reg52 <= slv_reg52;slv_reg53 <= slv_reg53;slv_reg54 <= slv_reg54;slv_reg55 <= slv_reg55;slv_reg56 <= slv_reg56;slv_reg57 <= slv_reg57;slv_reg58 <= slv_reg58;slv_reg59 <= slv_reg59;slv_reg60 <= slv_reg60;slv_reg61 <= slv_reg61;slv_reg62 <= slv_reg62;slv_reg63 <= slv_reg63;endendcaseendendend    // Implement write response logic generation// The write response and response valid signals are asserted by the slave // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  // This marks the acceptance of address and indicates the status of // write transaction.always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_bvalid  <= 0;axi_bresp   <= 2'b0;end elsebegin    if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)begin// indicates a valid write response is availableaxi_bvalid <= 1'b1;axi_bresp  <= 2'b0; // 'OKAY' response end                   // work error responses in futureelsebeginif (S_AXI_BREADY && axi_bvalid) //check if bready is asserted while bvalid is high) //(there is a possibility that bready is always asserted high)   beginaxi_bvalid <= 1'b0; end  endendend   // Implement axi_arready generation// axi_arready is asserted for one S_AXI_ACLK clock cycle when// S_AXI_ARVALID is asserted. axi_awready is // de-asserted when reset (active low) is asserted. // The read address is also latched when S_AXI_ARVALID is // asserted. axi_araddr is reset to zero on reset assertion.always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_arready <= 1'b0;axi_araddr  <= 32'b0;end elsebegin    if (~axi_arready && S_AXI_ARVALID)begin// indicates that the slave has acceped the valid read addressaxi_arready <= 1'b1;// Read address latchingaxi_araddr  <= S_AXI_ARADDR;endelsebeginaxi_arready <= 1'b0;endend end       // Implement axi_arvalid generation// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both // S_AXI_ARVALID and axi_arready are asserted. The slave registers // data are available on the axi_rdata bus at this instance. The // assertion of axi_rvalid marks the validity of read data on the // bus and axi_rresp indicates the status of read transaction.axi_rvalid // is deasserted on reset (active low). axi_rresp and axi_rdata are // cleared to zero on reset (active low).  always @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_rvalid <= 0;axi_rresp  <= 0;end elsebegin    if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)begin// Valid read data is available at the read data busaxi_rvalid <= 1'b1;axi_rresp  <= 2'b0; // 'OKAY' responseend   else if (axi_rvalid && S_AXI_RREADY)begin// Read data is accepted by the masteraxi_rvalid <= 1'b0;end                endend    // Implement memory mapped register select and read logic generation// Slave register read enable is asserted when valid address is available// and the slave is ready to accept the read address.assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;always @(*)begin// Address decoding for reading registersreg_data_out <= reg_rd_data;// case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )// 6'h00   : reg_data_out <= 32'h55aa_0001;// 6'h01   : reg_data_out <= slv_reg1;// 6'h02   : reg_data_out <= slv_reg2;// 6'h03   : reg_data_out <= slv_reg3;// 6'h04   : reg_data_out <= slv_reg4;// 6'h05   : reg_data_out <= slv_reg5;// 6'h06   : reg_data_out <= slv_reg6;// 6'h07   : reg_data_out <= slv_reg7;// 6'h08   : reg_data_out <= slv_reg8;// 6'h09   : reg_data_out <= slv_reg9;// 6'h0A   : reg_data_out <= slv_reg10;// 6'h0B   : reg_data_out <= slv_reg11;// 6'h0C   : reg_data_out <= slv_reg12;// 6'h0D   : reg_data_out <= slv_reg13;// 6'h0E   : reg_data_out <= slv_reg14;// 6'h0F   : reg_data_out <= slv_reg15;// 6'h10   : reg_data_out <= slv_reg16;// 6'h11   : reg_data_out <= slv_reg17;// 6'h12   : reg_data_out <= slv_reg18;// 6'h13   : reg_data_out <= slv_reg19;// 6'h14   : reg_data_out <= slv_reg20;// 6'h15   : reg_data_out <= slv_reg21;// 6'h16   : reg_data_out <= slv_reg22;// 6'h17   : reg_data_out <= slv_reg23;// 6'h18   : reg_data_out <= slv_reg24;// 6'h19   : reg_data_out <= slv_reg25;// 6'h1A   : reg_data_out <= slv_reg26;// 6'h1B   : reg_data_out <= slv_reg27;// 6'h1C   : reg_data_out <= slv_reg28;// 6'h1D   : reg_data_out <= slv_reg29;// 6'h1E   : reg_data_out <= slv_reg30;// 6'h1F   : reg_data_out <= reg_rd_data;//// 6'h20   : reg_data_out <= slv_reg32;// 6'h21   : reg_data_out <= slv_reg33;// 6'h22   : reg_data_out <= slv_reg34;// 6'h23   : reg_data_out <= slv_reg35;// 6'h24   : reg_data_out <= slv_reg36;// 6'h25   : reg_data_out <= slv_reg37;// 6'h26   : reg_data_out <= slv_reg38;// 6'h27   : reg_data_out <= slv_reg39;// 6'h28   : reg_data_out <= slv_reg40;// 6'h29   : reg_data_out <= slv_reg41;// 6'h2A   : reg_data_out <= slv_reg42;// 6'h2B   : reg_data_out <= slv_reg43;// 6'h2C   : reg_data_out <= slv_reg44;// 6'h2D   : reg_data_out <= slv_reg45;// 6'h2E   : reg_data_out <= slv_reg46;// 6'h2F   : reg_data_out <= slv_reg47;// 6'h30   : reg_data_out <= slv_reg48;// 6'h31   : reg_data_out <= slv_reg49;// 6'h32   : reg_data_out <= slv_reg50;// 6'h33   : reg_data_out <= slv_reg51;// 6'h34   : reg_data_out <= slv_reg52;// 6'h35   : reg_data_out <= slv_reg53;// 6'h36   : reg_data_out <= slv_reg54;// 6'h37   : reg_data_out <= slv_reg55;// 6'h38   : reg_data_out <= slv_reg56;// 6'h39   : reg_data_out <= slv_reg57;// 6'h3A   : reg_data_out <= slv_reg58;// 6'h3B   : reg_data_out <= slv_reg59;// 6'h3C   : reg_data_out <= slv_reg60;// 6'h3D   : reg_data_out <= slv_reg61;// 6'h3E   : reg_data_out <= slv_reg62;// 6'h3F   : reg_data_out <= slv_reg63;// default : reg_data_out <= 0;// endcaseend// Output register or memory read dataalways @( posedge S_AXI_ACLK )beginif ( S_AXI_ARESETN == 1'b0 )beginaxi_rdata  <= 0;end elsebegin    // When there is a valid read address (S_AXI_ARVALID) with // acceptance of read address by the slave (axi_arready), // output the read dada if (slv_reg_rden)beginaxi_rdata <= reg_data_out;     // register read dataend   endend    // Add user logic here
assign reg_wr_addr = axi_awaddr[7:2];
assign reg_rd_addr = S_AXI_ARADDR[7:2];
//assign reg_rd_addr = axi_araddr[7:2];
assign reg_wr_en = slv_reg_wren;
assign reg_wr_data = S_AXI_WDATA;
assign reg_rd_en = slv_reg_rden;// User logic endsendmodule
更改后IP配置有所变化，如下图所示：