Verilog刷题笔记54

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题目：
Fsm serialdp
See also: Serial receiver and datapath

We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.

官方提供的例化程序：

module parity (input clk,input reset,input in,output reg odd);always @(posedge clk)if (reset) odd <= 0;else if (in) odd <= ~odd;endmodule解题:
module top_module(input clk,input in,input reset,    // Synchronous resetoutput [7:0] out_byte,output done
); //parameter idle=0,data_receive=1,check=2,stop=3,error=4;reg [2:0]state,next_state;reg [7:0]data;wire odd_temp,start;reg [3:0]cnt;reg jo;parity parity_inst(.clk(clk),.reset(reset|start),.in(in),.odd(odd_temp));always@(posedge clk)beginif(reset)state<=idle;elsestate<=next_state;endalways@(*)beginstart=0;case(state)idle:begin next_state=in?idle:data_receive;start=1;enddata_receive:next_state=(cnt==8)?check:data_receive;check:next_state=in?stop:error;stop:begin next_state=in?idle:data_receive;start=1;enderror:next_state=in?idle:error;endcaseendalways@(posedge clk)beginif(reset)cnt<=0;else case(state)data_receive:cnt<=cnt+1;default:cnt<=0;endcaseendalways@(posedge clk)beginif(reset)data<=0;else case(next_state)data_receive:data<={in,data[7:1]};endcaseendalways@(posedge clk)beginif(reset)jo<=0;elsejo<=odd_temp;endassign out_byte=data;assign done=jo&(state==stop);// Modify FSM and datapath from Fsm_serialdata// New: Add parity checking.endmodule

结果正确：

总结：
多了个奇偶校验
为了方便例化程序的重新启用，所以减去了一个start状态，直接将start定义成一个变量。

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