本文主要是介绍RAM + 串口的简单应用，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
REVIEW
| 之前已经学习过： RAM： RAM IP核配置_ip核 ram配置-CSDN博客 串口接收：Vivado 串口接收优化-CSDN博客 串口发送：Vivado 串口通信(UART)------串口发送_vivado串口收发实验-CSDN博客 按键：基于状态机的按键消抖实现-CSDN博客 按键+串口发送实验_串口发按键值-CSDN博客 |
1. 今日摸鱼任务
| 小梅哥教材：02_【逻辑教程】基于HDL的FPGA逻辑设计与验证教程V3.4.pdf 15 搭建串口收发与存储双口 RAM 简易应用系统 |
| 实现：串口写入RAM，按键控制串口发送RAM中的数据 |
2. 系统框图
| 系统框图如下图： （其中baud_set[2:0]，摸鱼怪是直接改的波特率） （俺下载的这版还有小错误嘎嘎嘎~右下角应该是串口发送tx） |
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| 分析： 绿色：已封装好的模块 黄色：添加RAM IP核 红色ctrl：编写ctrl模块 总：写顶层 |
3. RAM配置
| RAM： RAM IP核配置_ip核 ram配置-CSDN博客 使用的是无ena 、enb第一版 |
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4. RX + RAM
uartrx.v |
| 区别于之前的程序，使rx_data提前于rx_done一个clk |
| module uartrx(
input clk ,
input reset_n ,
input uart_rx ,
output reg [7:0]rx_data,
output reg rx_done );
//默认使用波特率BAUD 115200 时钟频率 CLK_FREQ 50MHz
// parameter start_bit = 0 ;
// parameter stop_bit = 1 ;
parameter BAUD = 9600;
parameter CLK_FREQ = 50_000_000;
parameter bps_c = CLK_FREQ / BAUD ;
reg rx_en ;
reg[3:0] rx_flag;
// bps
reg [30:0] counter_bps ;
always@(posedge clk or negedge reset_n)
if(! reset_n)
counter_bps <= 0 ;
else if (rx_en)
if(counter_bps == bps_c - 1)
counter_bps <= 0 ;
else
counter_bps <= counter_bps + 1'b1 ;
else
counter_bps <= 0 ;
reg dff_rx_0 , dff_rx_1 ;
reg r_uart_rx;
wire neg_rx_go ;
always@(posedge clk )
dff_rx_0 <= uart_rx ;
always@(posedge clk )
dff_rx_1 <= dff_rx_0 ;
always@(posedge clk )
r_uart_rx <= dff_rx_1 ;
assign neg_rx_go = (dff_rx_1 == 0)&&(r_uart_rx == 1);
// rx_en
always@(posedge clk or negedge reset_n)
if(! reset_n)
rx_en <= 0 ;
else if(neg_rx_go)
rx_en <= 1 ;
else if((rx_flag==9)&&(counter_bps == bps_c / 2))
rx_en <= 0 ;
else if((rx_flag==0)&&(counter_bps == bps_c/2 )&&(dff_rx_1==1))
rx_en <= 0 ;
// rx_flag
always@(posedge clk or negedge reset_n)
if(!reset_n) rx_flag <= 4'b0000 ;
else if((rx_flag == 9)&&(counter_bps == bps_c /2)) rx_flag <= 4'b0000 ;
else if(counter_bps == bps_c - 1) rx_flag <= rx_flag + 1'b1 ;
// [7:0]r_rx_data
reg [7:0] r_rx_data;
always@(posedge clk )
if(!rx_en) r_rx_data <= r_rx_data;
else if(counter_bps == bps_c / 2)
begin
case(rx_flag)
1 : r_rx_data[0] <= dff_rx_1;
2 : r_rx_data[1] <= dff_rx_1;
3 : r_rx_data[2] <= dff_rx_1;
4 : r_rx_data[3] <= dff_rx_1;
5 : r_rx_data[4] <= dff_rx_1;
6 : r_rx_data[5] <= dff_rx_1;
7 : r_rx_data[6] <= dff_rx_1;
8 : r_rx_data[7] <= dff_rx_1;
default : r_rx_data <= r_rx_data;
endcase
end
// rx_done
always@(posedge clk)
rx_done <= (rx_flag==9)&&(counter_bps == bps_c /2);
// rx_data ;
always@(posedge clk)
if((rx_flag==9)&&(counter_bps == bps_c /2 -1)) rx_data <= r_rx_data;
endmodule |
rx_ram_00.v |
| module rx_ram_00(
input clk ,
input reset_n ,
input uart_rx ,
input clkb ,
input[7 : 0]addrb ,
output [7 : 0] doutb
);
wire rx_done;
wire [7:0]rx_data;
reg [7:0]addra; ram ram_ (
.clka(clk), // input wire clka
.wea(rx_done), // input wire [0 : 0] wea
.addra(addra), // input wire [7 : 0] addra
.dina(rx_data), // input wire [7 : 0] dina
.clkb(clkb), // input wire clkb
.addrb(addrb), // input wire [7 : 0] addrb
.doutb(doutb) // output wire [7 : 0] doutb
);
uartrx uart_rx_(
. clk(clk) ,
. reset_n(reset_n) ,
. uart_rx(uart_rx) ,
. rx_data(rx_data),
. rx_done(rx_done) );
always@(posedge clk or negedge reset_n)
if(!reset_n)
addra <= 8'B0000_0000;
else if(rx_done)
addra <= addra + 1'b1;
endmodule |
rx_tb.v |
`timescale 1ns / 1ns
module rx_tb();
reg clk , reset_n ;
reg uart_rx;
reg clkb;
reg [7:0]addrb;
wire [7:0]doutb;
integer i;
rx_ram_00 rx_ram_00_(
. clk(clk) ,
. reset_n(reset_n) ,
. uart_rx(uart_rx) ,
. clkb(clkb) ,
. addrb(addrb) ,
. doutb(doutb)
);
initial clk = 1 ;
always #10 clk = ~clk ;
initial clkb = 1 ;
always #20 clkb = ~clkb ;
initial
begin
reset_n = 0 ;
uart_rx = 1 ;
addrb = 255;
i = 0 ;
#201;
reset_n = 1 ; #2000;
// F0 1111_0000
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// F0 1111_0000
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// F0 1111_0000
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
// F0 1111_0000
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20); uart_rx = 0 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20); uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20); #200000;
for (i = 0 ; i < 8 ; i = i+1)
begin
addrb = i;
#40;
end
addrb = 255;
#2000;
$stop;
end
endmodule |
| 
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| 
|
| 测试了向RAM中写入8个数据，并读出 |
| 由图可以看出串口写入模块正常 |
| 摸鱼怪碎碎念：之前 always@(posedge clk or negedge reset_n)
if(!reset_n)
addra <= 8'B0000_0000;
else if(rx_done)
addra <= addra + 1'b1; always@(posedge clk)
if((rx_flag==9)&&(counter_bps == bps_c /2 -1)) rx_data <= r_rx_data; 这两部分调试出来滴，之前没有连续传输过，so没注意到这个问题，嘿嘿嘿~ |
5. RX + RAM +Key + TX
key_one.v |
| module key_one(
input clk ,
input reset_n,
input key,
output reg key_flag,
output reg key_state);
// nedge_key pedge_key
reg dff_k_0 , dff_k_1 ;
reg r_key;
wire nedge_key, pedge_key;
always@(posedge clk )
dff_k_0 <= key ;
always@(posedge clk )
dff_k_1 <= dff_k_0 ;
always@(posedge clk )
r_key <= dff_k_1 ;
assign nedge_key = (r_key == 1)&&(dff_k_1 == 0);
assign pedge_key = (r_key == 0)&&(dff_k_1 == 1);
// key_now 0:IDLE 1:FILTER0 2:DOWN 3:FILTER1
// cnt 20ms/20ns = 1000000 ;
reg [1:0]key_now;
reg [19:0] cnt;
parameter cnt_N = 1000; //测试的时候为了速度快一点调成这个，当然之前参数化有学习过应该咋做 //摸鱼怪是这样的(确信 //上板记得改回6个0
always@(posedge clk or negedge reset_n )
if(!reset_n)
begin
key_now <= 0 ;
cnt <= 0;
key_flag <= 0;
key_state <= 1;
end
else
begin
key_flag <= 0;
case(key_now)
0:
if(!nedge_key) key_now <= 0;
else
begin
cnt <= 0 ;
key_now <= 1;
end
1:
if(pedge_key) key_now <= 0;
else if(cnt >= cnt_N - 1)
begin
cnt <= 0 ;
key_now <= 2;
key_flag <= 1;
key_state <= 0;
end
else cnt <= cnt + 1'b1;
2:
if(!pedge_key) key_now <= 2;
else
begin
cnt <= 0 ;
key_now <= 3;
end
3:
if(nedge_key) key_now <= 2;
else if(cnt >= cnt_N - 1)
begin
cnt <= 0 ;
key_now <= 0;
key_flag <= 1;
key_state <= 1;
end
else cnt <= cnt + 1'b1;
endcase
end endmodule |
uarttx.v |
| module uarttx(input clk ,
input reset_n ,
input [7:0]data ,
input Send_Go ,
output reg uart_tx ,
output reg tx_done );
//默认使用波特率BAUD 9600 时钟频率 CLK_FREQ 50MHz
parameter start_bit = 0 ;
parameter stop_bit = 1 ;
parameter BAUD = 9600;
parameter CLK_FREQ = 50_000_000;
parameter bps_c = CLK_FREQ / BAUD ;
reg Send_en ;
always@(posedge clk or negedge reset_n )
if(! reset_n)
Send_en <= 0 ;
else if(Send_Go)
Send_en <= 1 ;
else if((tx_flag==9)&&(counter_bps == bps_c - 1))
Send_en <= 0 ;
// bps
reg [30:0] counter_bps ;
always@(posedge clk or negedge reset_n)
if(! reset_n)
counter_bps <= 0 ;
else if (Send_en)
if(counter_bps == bps_c - 1)
counter_bps <= 0 ;
else
counter_bps <= counter_bps + 1'b1 ;
else
counter_bps <= 0 ;
// 发送状态
reg [3:0] tx_flag;
always@(posedge clk or negedge reset_n)
if(! reset_n)
tx_flag <= 0 ;
else if (!Send_en) tx_flag <= 0 ;
else if ((tx_flag==9)&&(counter_bps == bps_c - 1))
tx_flag <= 0 ;
else
if(counter_bps == bps_c - 1)
tx_flag <= tx_flag + 1'b1 ;
// Send_Go改变发送信号
reg [7:0]r_data;
always@(posedge clk)
if(Send_Go)
r_data <= data;
else
r_data <= r_data;
// tx_flag
always@(*)
if(!Send_en) uart_tx <= 1'b1;
else
begin
case(tx_flag)
4'b0000 : uart_tx <= start_bit;
4'b0001 : uart_tx <= r_data[0];
4'b0010 : uart_tx <= r_data[1];
4'b0011 : uart_tx <= r_data[2];
4'b0100 : uart_tx <= r_data[3];
4'b0101 : uart_tx <= r_data[4];
4'b0110 : uart_tx <= r_data[5];
4'b0111 : uart_tx <= r_data[6];
4'b1000 : uart_tx <= r_data[7];
4'b1001 : uart_tx <= stop_bit;
default : uart_tx <= uart_tx;
endcase
end
always@(posedge clk )
tx_done <= (tx_flag==9)&&(counter_bps == bps_c - 1);
endmodule |
rx_ram_tx.v（第一版） |
| module rx_ram_tx(
input clk ,
input reset_n ,
input uart_rx ,
input key ,
output uart_tx
);
wire rx_done;
wire [7:0]rx_data;
reg [7:0]addra;
reg [7:0]addrb;
wire [7:0]doutb;
wire key_flag;
wire key_state;
wire tx_done;
ram ram_ (
.clka(clk), // input wire clka
.wea(rx_done), // input wire [0 : 0] wea
.addra(addra), // input wire [7 : 0] addra
.dina(rx_data), // input wire [7 : 0] dina
.clkb(clk), // input wire clkb
.addrb(addrb), // input wire [7 : 0] addrb
.doutb(doutb) // output wire [7 : 0] doutb
);
uartrx uart_rx_(
. clk(clk) ,
. reset_n(reset_n) ,
. uart_rx(uart_rx) ,
. rx_data(rx_data),
. rx_done(rx_done) );
always@(posedge clk or negedge reset_n)
if(!reset_n)
addra <= 8'b0000_0000;
else if(rx_done)
addra <= addra + 1'b1;
key_one key_(
. clk(clk) ,
. reset_n(reset_n),
. key(key),
. key_flag(key_flag),
. key_state(key_state)
);
always@(posedge clk or negedge reset_n)
if(!reset_n)
addrb <= 8'b0000_0000;
else if(tx_done)
addrb <= addrb + 1'b1;
//这其实是是有问题滴！！！
reg tx_en ;
always@(posedge clk or negedge reset_n)
if(!reset_n)
tx_en <= 1'b0 ;
else if((key_flag)&&(key_state==0))
tx_en <= 1'b1;
else if(addrb == 11) //这里也是因为测试才这样写滴
tx_en <= 1'b0 ;
reg Send_Go ;
always@(posedge clk or negedge reset_n)
if(!reset_n)
Send_Go <= 1'b0 ;
else if((key_flag)&&(key_state==0))
Send_Go <= 1'b1;
else if(tx_en && tx_done)
Send_Go <= 1'b1 ;
else
Send_Go <= 1'b0 ; //为什么跟addrb 同样的颜色捏~
uarttx uart_tx_(
. clk(clk) ,
. reset_n(reset_n) ,
. data(doutb) ,
. Send_Go(Send_Go) ,
. uart_tx(uart_tx) ,
. tx_done(tx_done)
);
endmodule |
rx_ram_key_tx_tb.v |
| `timescale 1ns / 1ns module rx_ram_key_tx_tb( );
reg clk ;
reg reset_n ;
reg uart_rx ;
reg key ;
wire uart_tx ;
rx_ram_tx rx_ram_tx_(
. clk(clk) ,
. reset_n(reset_n) ,
. uart_rx(uart_rx) ,
. key(key) ,
. uart_tx(uart_tx)
);
initial clk = 1 ;
always#10 clk = ~clk ;
initial
begin
reset_n = 0 ;
uart_rx = 1 ;
key = 1'b1 ;
#201;
reset_n = 1 ; #2000;
// 0F 0000_1111
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 0F 0000_1111
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 0F 0000_1111
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 55 0101_0101
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
// 0F 0000_1111
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 0 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
uart_rx = 1 ; #(5208*20);
#200000;
key_press(2);
#(5208*20*8*20);
$stop;
end
reg [13:0] rand;
task key_press;
input[3:0]seed;
begin
key = 1'b1 ;
#1000;
repeat(10)
begin
rand = {$random(seed)} % 10000;
#rand;
key=~key;
end
key = 1'b0 ;
#100000;
key = 1'b1 ;
end
endtask
endmodule |
| 
|
| 嘎嘎嘎~是不是觉得貌似没有问题~ 那为什么要说存在问题捏！ 自行调试一下： always@(posedge clk or negedge reset_n)
if(!reset_n)
addrb <= 8'b1111_1111;
else if((key_flag)&&(key_state==0))
addrb <= 8'b0000_0000;
else if(tx_done)
addrb <= addrb + 1'b1; （俺这里没有保存，就是之前学习RAM读取，配置中存在一个Latentcy |
rx_ram_tx.v（修改后） |
| module rx_ram_tx(
input clk ,
input reset_n ,
input uart_rx ,
input key ,
output uart_tx
);
wire rx_done;
wire [7:0]rx_data;
reg [7:0]addra;
reg [7:0]addrb;
wire [7:0]doutb;
wire key_flag;
wire key_state;
wire tx_done;
ram ram_ (
.clka(clk), // input wire clka
.wea(rx_done), // input wire [0 : 0] wea
.addra(addra), // input wire [7 : 0] addra
.dina(rx_data), // input wire [7 : 0] dina
.clkb(clk), // input wire clkb
.addrb(addrb), // input wire [7 : 0] addrb
.doutb(doutb) // output wire [7 : 0] doutb
);
uartrx uart_rx_(
. clk(clk) ,
. reset_n(reset_n) ,
. uart_rx(uart_rx) ,
. rx_data(rx_data),
. rx_done(rx_done) );
always@(posedge clk or negedge reset_n)
if(!reset_n)
addra <= 8'b0000_0000;
else if(rx_done)
addra <= addra + 1'b1;
key_one key_(
. clk(clk) ,
. reset_n(reset_n),
. key(key),
. key_flag(key_flag),
. key_state(key_state)
);
always@(posedge clk or negedge reset_n)
if(!reset_n)
addrb <= 8'b1111_1111;
else if((key_flag)&&(key_state==0)) //发送从首地址开始
addrb <= 8'b0000_0000;
else if(tx_done)
addrb <= addrb + 1'b1;
reg tx_en ;
always@(posedge clk or negedge reset_n)
if(!reset_n)
tx_en <= 1'b0 ;
else if((key_flag)&&(key_state==0))
tx_en <= 1'b1;
else if(addrb == 11)
tx_en <= 1'b0 ;
reg Send_Go_0 , Send_Go_1 ,Send_Go_2 ,Send_Go ; //这部分是之前的Send_Go
always@(posedge clk or negedge reset_n)
if(!reset_n)
Send_Go_0 <= 1'b0 ;
else if((key_flag)&&(key_state==0))
Send_Go_0 <= 1'b1;
else if(tx_en && tx_done)
Send_Go_0 <= 1'b1 ;
else
Send_Go_0 <= 1'b0 ;
//这部分是Latentcy
always@(posedge clk or negedge reset_n)
if(!reset_n)
begin
Send_Go_1 <= 1'b0 ;
Send_Go_2 <= 1'b0 ;
Send_Go <= 1'b0 ;
end
else
begin
Send_Go_1 <= Send_Go_0 ;
Send_Go_2 <= Send_Go_1 ;
Send_Go <= Send_Go_2 ;
end
uarttx uart_tx_(
. clk(clk) ,
. reset_n(reset_n) ,
. data(doutb) ,
. Send_Go(Send_Go) ,
. uart_tx(uart_tx) ,
. tx_done(tx_done)
);
endmodule |
 |
 |
6. 板级验证
.xdc |
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports key]
set_property IOSTANDARD LVCMOS33 [get_ports reset_n]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
set_property PACKAGE_PIN U18 [get_ports clk]
set_property PACKAGE_PIN H18 [get_ports key]
set_property PACKAGE_PIN H20 [get_ports reset_n]
set_property PACKAGE_PIN K16 [get_ports uart_rx]
set_property PACKAGE_PIN J16 [get_ports uart_tx] |
| 依次向RAM中写入：0x10~0x1F(一开始把0忘记哩~)读取到的数值是正确的 但是写入：0x01~0xF1 可以看出，最高两位的数据一直为0 |
 |
| 存在的小错误下次继续调试叭~ 摸鱼怪跑路~ |
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