10G MAC层设计系列-（3）CRC Process 模块

本文主要是介绍10G MAC层设计系列-（3）CRC Process 模块，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！

一、前言

前面已经讲述了在Xilinx 10G PCS/PMA IP核的基础上设计的PHY层，已经xgmii接口的MAC_RX模块，本节主要描述MAC_RX之后的CRC_Process模块。

CRC_Prcess的主要作用就是利用RAM地址“返回初始状态”的方式将crc错误的帧丢掉，并将正确的传递到上级。

二、模块设计

首先，将数据帧、最后一次传输的KEEP信号存入RAM

BRAM_DATA_64X512 u_BRAM_DATA_64X512 (.clka     (i_clk                  ),    // input wire clka.wea      (rs_axis_valid          ),      // input wire [0 : 0] wea.addra    (r_bram_wdata_addr      ),  // input wire [8 : 0] addra.dina     (rs_axis_data           ),    // input wire [63 : 0] dina.clkb     (i_clk                  ),    // input wire clkb.enb      (r_bram_data_rden       ),      // input wire enb.addrb    (r_bram_rdata_addr      ),  // input wire [8 : 0] addrb.doutb    (w_bram_data_out        )  // output wire [63 : 0] doutb
);//将每一帧的最后一次传输的KEEP信号存入到RAM
BRAM_KEEP_8X128 your_instance_name (.clka     (i_clk                  ),    // input wire clka.wea      (rs_axis_last           ),      // input wire [0 : 0] wea.addra    (r_bram_wkeep_addr      ),  // input wire [6 : 0] addra.dina     (rs_axis_keep           ),    // input wire [7 : 0] dina.clkb     (i_clk                  ),    // input wire clkb.enb      (r_bram_keep_rden       ),      // input wire enb.addrb    (r_bram_rkeep_addr      ),  // input wire [6 : 0] addrb.doutb    (w_bram_rkeep           )  // output wire [7 : 0] doutb
);

在此过程中存在一个初始化的地址信号，只有检测到CRC校验正确之后才会更新初始的地址信号。

//写数据初始化地址，当CRC校验正确的时候才会改变
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_init_wdata_addr <= 'd0;else if(w_crc_correct)r_init_wdata_addr <= r_bram_wdata_addr + 1;elser_init_wdata_addr <= r_init_wdata_addr;
end
//写数据地址
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_wdata_addr <= 'd0;elseif(s_axis_valid && !rs_axis_valid)r_bram_wdata_addr <= r_init_wdata_addr;else if(rs_axis_valid && !rs_axis_last)r_bram_wdata_addr <= r_bram_wdata_addr + 1;elser_bram_wdata_addr <= r_bram_wdata_addr;
end
//写KEEP信号的初始化地址，当CRC校验正确的时候才会改变
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_init_wkeep_addr <= 'd0;elseif(w_crc_correct)r_init_wkeep_addr <= r_bram_wkeep_addr + 1;elser_init_wkeep_addr <= r_init_wkeep_addr;        
end
//写KEEP信号地址
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_wkeep_addr <= 'd0;elseif(s_axis_last)r_bram_wkeep_addr <= r_init_wkeep_addr;elser_bram_wkeep_addr <= r_bram_wkeep_addr;
end

最后的帧长等信息只有在CRC校验正确之后存入FIFO，用FIFO的empty信号判断RAM中是否有正确的数据。

FIFO_USER_INFO_80X128 u_FIFO_USER_INFO_80X128 (.clk      (i_clk                  ),      // input wire clk.srst     (i_rst                  ),    // input wire srst.din      (r_user_info            ),      // input wire [79 : 0] din.wr_en    (w_crc_correct          ),  // input wire wr_en.rd_en    (r_fifo_user_info_rden  ),  // input wire rd_en.dout     (w_fifo_user_out        ),    // output wire [79 : 0] dout.full     (w_fifo_user_info_full  ),    // output wire full.empty    (w_fifo_user_info_empty )  // output wire empty
);

在读数据的过程中，便是根据FIFO是否为空判断是否有有效数据，之后读出FIFO帧长等信息，根据帧长去读取RAM中的数据。

//读取USER_INFO FIFO中的信息
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_fifo_user_info_rden <= 'd0;elseif(!w_fifo_user_info_empty && !r_fifo_rden_lock)r_fifo_user_info_rden <= 1'b1;elser_fifo_user_info_rden <= 1'b0;
end
//锁存信号
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_fifo_rden_lock <= 'd0;else if(!w_fifo_user_info_empty)r_fifo_rden_lock <= 1'b1;else if(rm_axis_last)r_fifo_rden_lock <= 1'b0;elser_fifo_rden_lock <= r_fifo_rden_lock; 
end
//读USER INFO
always@(posedge i_clk,posedge i_rst)beginif(i_rst)rm_axis_user <= 'd0;elserm_axis_user <= w_fifo_user_out;
end//读数据的使能慢读USER INFO的使能一拍
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_data_rden <= 'd0;elseif(r_fifo_user_info_rden)r_bram_data_rden <= 1'b1;else if(r_data_cnt == w_fifo_user_out[79:64])r_bram_data_rden <= 'd0;elser_bram_data_rden <= r_bram_data_rden;
end
//读数据地址
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_rdata_addr <= 'd0;elseif(r_fifo_user_info_rden)r_bram_rdata_addr <= r_init_rdata_addr;else if((r_data_cnt < w_fifo_user_out[79:64]) && r_data_cnt)r_bram_rdata_addr <= r_bram_rdata_addr + 1;elser_bram_rdata_addr <= r_bram_rdata_addr ;
endalways@(posedge i_clk,posedge i_rst)beginif(i_rst)r_init_rdata_addr <= 'd0;else    if((r_data_cnt == w_fifo_user_out[79:64]) && r_bram_data_rden)r_init_rdata_addr <= r_bram_rdata_addr + 1;elser_init_rdata_addr <= r_init_rdata_addr;
endalways@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_data_rden_ff1 <= 'd0; elser_bram_data_rden_ff1 <= r_bram_data_rden;
end
//读keep使能
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_keep_rden <= 1'b0;elseif(r_data_cnt == w_fifo_user_out[79:64] -1)r_bram_keep_rden <= 1'b1;else r_bram_keep_rden <= 1'b0;
endalways@(posedge i_clk,posedge i_rst)beginif(i_rst)r_bram_rkeep_addr <= 'd0;else    if(r_data_cnt == w_fifo_user_out[79:64] -1)r_bram_rkeep_addr <= r_init_rkeep_addr;else r_bram_rkeep_addr <= r_bram_rkeep_addr;        
endalways@(posedge i_clk,posedge i_rst)beginif(i_rst)r_init_rkeep_addr <= 'd0;else    if((r_data_cnt == w_fifo_user_out[79:64]) && r_data_cnt)r_init_rkeep_addr <= r_bram_rkeep_addr + 1;else r_init_rkeep_addr <= r_init_rkeep_addr;        
end//寻找上升沿
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_data_rden_pos <= 'd0; elseif(r_bram_data_rden && !r_bram_data_rden_ff1)r_data_rden_pos <= 1'b1;elser_data_rden_pos <= 1'b0;
end
//寻找下降沿
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_data_rden_nge <= 'd0; elseif(!r_bram_data_rden && r_bram_data_rden_ff1)r_data_rden_nge <= 1'b1;elser_data_rden_nge <= 1'b0;
end
//读数据计数
always@(posedge i_clk,posedge i_rst)beginif(i_rst)r_data_cnt <= 'd0;elseif(r_fifo_user_info_rden || r_bram_data_rden)r_data_cnt <= r_data_cnt + 1;elser_data_cnt <= 'd0;
end
//数据转换成AXIS接口输出
always@(posedge i_clk,posedge i_rst)beginif(i_rst)rm_axis_data <= 'd0;elserm_axis_data <= w_bram_data_out;
end
//Valid信号
always@(posedge i_clk,posedge i_rst)beginif(i_rst)rm_axis_valid <= 1'b0;elseif(rm_axis_last)rm_axis_valid <= 1'b0;else if(r_data_rden_pos)rm_axis_valid <= 1'b1;elserm_axis_valid <= rm_axis_valid;
end
//Last信号
always@(posedge i_clk,posedge i_rst)beginif(i_rst)rm_axis_last <= 'd0;elseif(!r_bram_data_rden && r_bram_data_rden_ff1)rm_axis_last <= 1'b1;elserm_axis_last <= 1'b0;
end
//KEEP信号
always@(posedge i_clk,posedge i_rst)beginif(i_rst)rm_axis_keep <= 'd0;elseif(w_fifo_user_out[79:64] == 1 && r_data_rden_pos)rm_axis_keep <= w_bram_rkeep;else if(w_fifo_user_out[79:64] > 1 && r_data_rden_pos)rm_axis_keep <= 8'hff;else if(!r_bram_data_rden && r_bram_data_rden_ff1)rm_axis_keep <= w_bram_rkeep;elserm_axis_keep <= rm_axis_keep;
end