瑞萨单片机学习：RA4M3单片机 BOOTloader升级跳转到主程序主程序无法执行问题

本文主要是介绍瑞萨单片机学习：RA4M3单片机 BOOTloader升级跳转到主程序主程序无法执行问题，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！

背景：

使用瑞萨的RA4M3单片机编写BOOT引导程序进行测试，在BOOT程序跳转到主程序时，主程序无法执行。本文介绍了问题的定位和解决方法。

运行开发环境介绍

硬件环境

RA4M3 官方开发板

J-LINK V11 开发板自带

软件开发环境

e2 studio

VSCODE

软件支持包

灵活配置软件包 FSP 安装

一开始从BOOT更新了APP FLASH后，然后跳转主程序APP地址，发现程序无法执行，注释掉下面的代码就可以。

SystemInit()

但是这样系统时钟没有经过初始化，延时函数会出问题。

后来经过挨着注释最好发现注释掉函数里的下面这行就能跳转了。

    /* Call Post C runtime initialization hook. */// R_BSP_WarmStart(BSP_WARM_START_POST_C);

/*******************************************************************************************************************//*** Initialize the MCU and the runtime environment.**********************************************************************************************************************/
void SystemInit (void)
{
//    *__Vectors =  (uint32_t * )0x00038000;
#if __FPU_USED/* Enable the FPU only when it is used.* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) *//* Set bits 20-23 (CP10 and CP11) to enable FPU. */SCB->CPACR = (uint32_t) CP_MASK;
#endif#if BSP_TZ_SECURE_BUILD/* Seal the main stack for secure projects. Reference:* https://developer.arm.com/documentation/100720/0300* https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */uint32_t * p_main_stack_top = (uint32_t *) __Vectors[0];*p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE;
#endif#if !BSP_TZ_NONSECURE_BUILD/* VTOR is in undefined state out of RESET:* https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en.* Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure* projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */
//    SCB->VTOR = (uint32_t) &__Vectors;SCB->VTOR = (uint32_t)&__Vectors;
#endif#if !BSP_TZ_CFG_SKIP_INIT#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP/* Unlock VBTCR1 register. */R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;/* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1* "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual* R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot* be accessed until VBTSR.VBTRVLD is set. */R_SYSTEM->VBTCR1 = 1U;FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U);/* Lock VBTCR1 register. */R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;#endif
#endif#if BSP_FEATURE_TFU_SUPPORTEDR_BSP_MODULE_START(FSP_IP_TFU, 0U);
#endif#if BSP_CFG_EARLY_INIT/* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */bsp_init_uninitialized_vars();
#endif/* Call pre clock initialization hook. */R_BSP_WarmStart(BSP_WARM_START_RESET);#if BSP_TZ_CFG_SKIP_INIT/* Initialize clock variables to be used with R_BSP_SoftwareDelay. */bsp_clock_freq_var_init();
#else/* Configure system clocks. */bsp_clock_init();#if BSP_FEATURE_BSP_RESET_TRNG/* To prevent an undesired current draw, this MCU requires a reset* of the TRNG circuit after the clocks are initialized */bsp_reset_trng_circuit();#endif
#endif/* Call post clock initialization hook. */R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);#if BSP_FEATURE_BSP_HAS_SP_MON/* Disable MSP monitoring  */R_MPU_SPMON->SP[0].CTL = 0;/* Setup NMI interrupt  */R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION;/* Setup start address  */R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT;/* Setup end address  */R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP;/* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need* to read-modify-write. */R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;/* Enable MSP monitoring  */R_MPU_SPMON->SP[0].CTL = 1U;
#endif#if BSP_FEATURE_TZ_HAS_TRUSTZONE/* Use CM33 stack monitor. */__set_MSPLIM(BSP_PRV_STACK_LIMIT);
//    __set_MSPLIM(0);
#endif#if BSP_CFG_C_RUNTIME_INIT/* Initialize C runtime environment. *//* Zero out BSS */#if defined(__ARMCC_VERSION)memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length);#elif defined(__GNUC__)memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__));#elif defined(__ICCARM__)memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss"));#endif/* Copy initialized RAM data from ROM to RAM. */#if defined(__ARMCC_VERSION)memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);#elif defined(__GNUC__)memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));#elif defined(__ICCARM__)memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),(uint32_t) __section_size(".data"));/* Copy functions to be executed from RAM. */#pragma section=".code_in_ram"#pragma section=".code_in_ram_init"memcpy((uint32_t *) __section_begin(".code_in_ram"),(uint32_t *) __section_begin(".code_in_ram_init"),(uint32_t) __section_size(".code_in_ram"));/* Copy main thread TLS to RAM. */#pragma section="__DLIB_PERTHREAD_init"#pragma section="__DLIB_PERTHREAD"memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),(uint32_t) __section_size("__DLIB_PERTHREAD_init"));#endif/* Initialize static constructors */#if defined(__ARMCC_VERSION)int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base;for (int32_t i = 0; i < count; i++){void (* p_init_func)(void) =(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);p_init_func();}#elif defined(__GNUC__)int32_t count = __init_array_end - __init_array_start;for (int32_t i = 0; i < count; i++){__init_array_start[i]();}#elif defined(__ICCARM__)void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");void const * ilimit = __section_end("SHT$$INIT_ARRAY");__call_ctors(pibase, ilimit);#endif
#endif                                 // BSP_CFG_C_RUNTIME_INIT/* Initialize SystemCoreClock variable. */SystemCoreClockUpdate();#if !BSP_CFG_PFS_PROTECT#if BSP_TZ_SECURE_BUILDR_PMISC->PWPRS = 0;                              ///< Clear BOWI bit - writing to PFSWE bit enabledR_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled#elseR_PMISC->PWPR = 0;                               ///< Clear BOWI bit - writing to PFSWE bit enabledR_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET;  ///< Set PFSWE bit - writing to PFS register enabled#endif
#endif#if FSP_PRIV_TZ_USE_SECURE_REGS/* Ensure that the PMSAR registers are reset (Soft reset does not reset PMSAR). */R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);for (uint32_t i = 0; i < 9; i++){R_PMISC->PMSAR[i].PMSAR = UINT16_MAX;}R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif#if BSP_TZ_SECURE_BUILD/* Initialize security features. */R_BSP_SecurityInit();
#endif/* Call Post C runtime initialization hook. */// R_BSP_WarmStart(BSP_WARM_START_POST_C);/* Initialize ELC events that will be used to trigger NVIC interrupts. */bsp_irq_cfg();/* Call any BSP specific code. No arguments are needed so NULL is sent. */bsp_init(NULL);
}