本文主要是介绍antlr4 Verilog2001.g4，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！
➜ verilog which antlr4
antlr4: aliased to java -Xmx500M -cp "/usr/local/lib/antlr-4.9-complete.jar:$CLASSPATH" org.antlr.v4.Tool
➜ verilog which grun
grun: aliased to java -Xmx500M -cp "/usr/local/lib/antlr-4.9-complete.jar:$CLASSPATH" org.antlr.v4.gui.TestRig
➜ verilog antlr4 Verilog2001.g4
➜ verilog javac *.java
➜ verilog grun Verilog2001 tokens -tokens examples/example1.v
[@0,0:5='module',<'module'>,1:0]
[@1,6:6=' ',<White_space>,channel=1,1:6]
[@2,7:16='SPI_MASTER',<Simple_identifier>,1:7]
[@3,17:17='(',<'('>,1:17]
[@4,18:22='\n ',<White_space>,channel=1,1:18]
[@5,23:27='input',<'input'>,2:4]
[@6,28:35=' ',<White_space>,channel=1,2:9]
[@7,36:38='clk',<Simple_identifier>,2:17]
[@8,39:43=' ',<White_space>,channel=1,2:20]
[@9,44:44=',',<','>,2:25]
[@10,45:45=' ',<White_space>,channel=1,2:26]
[@11,46:68='//the FPGA input clock\n',<One_line_comment>,channel=1,2:27]
[@12,69:72=' ',<White_space>,channel=1,3:0]
[@13,73:77='input',<'input'>,3:4]
[@14,78:85=' ',<White_space>,channel=1,3:9]
[@15,86:90='rst_n',<Simple_identifier>,3:17]
[@16,91:93=' ',<White_space>,channel=1,3:22]
[@17,94:94=',',<','>,3:25]
[@18,95:95=' ',<White_space>,channel=1,3:26]
[@19,96:125='//the FPGA asynchronous reset\n',<One_line_comment>,channel=1,3:27]
[@20,126:147=' \n ',<White_space>,channel=1,4:0]
[@21,148:152='input',<'input'>,5:4]
[@22,153:160=' ',<White_space>,channel=1,5:9]
[@23,161:167='spi_sdi',<Simple_identifier>,5:17]
[@24,168:168=' ',<White_space>,channel=1,5:24]
[@25,169:169=',',<','>,5:25]
[@26,170:170=' ',<White_space>,channel=1,5:26]
[@27,171:191='//the SPI read input\n',<One_line_comment>,channel=1,5:27]
[@28,192:195=' ',<White_space>,channel=1,6:0]
[@29,196:201='output',<'output'>,6:4]
[@30,202:202=' ',<White_space>,channel=1,6:10]
[@31,203:205='reg',<'reg'>,6:11]
[@32,206:208=' ',<White_space>,channel=1,6:14]
[@33,209:215='spi_sdo',<Simple_identifier>,6:17]
[@34,216:216=' ',<White_space>,channel=1,6:24]
[@35,217:217=',',<','>,6:25]
[@36,218:218=' ',<White_space>,channel=1,6:26]
[@37,219:241='//the SPI write output\n',<One_line_comment>,channel=1,6:27]
[@38,242:245=' ',<White_space>,channel=1,7:0]
[@39,246:251='output',<'output'>,7:4]
[@40,252:252=' ',<White_space>,channel=1,7:10]
[@41,253:255='reg',<'reg'>,7:11]
[@42,256:258=' ',<White_space>,channel=1,7:14]
[@43,259:265='spi_sck',<Simple_identifier>,7:17]
[@44,266:266=' ',<White_space>,channel=1,7:24]
[@45,267:267=',',<','>,7:25]
[@46,268:268=' ',<White_space>,channel=1,7:26]
[@47,269:284='//the SPI clock\n',<One_line_comment>,channel=1,7:27]
[@48,285:288=' ',<White_space>,channel=1,8:0]
[@49,289:294='output',<'output'>,8:4]
[@50,295:295=' ',<White_space>,channel=1,8:10]
[@51,296:298='reg',<'reg'>,8:11]
[@52,299:301=' ',<White_space>,channel=1,8:14]
[@53,302:307='spi_cs',<Simple_identifier>,8:17]
[@54,308:311=' ',<White_space>,channel=1,8:23]
[@55,312:336='//the SPI chip selection\n',<One_line_comment>,channel=1,8:27]
[@56,337:337=')',<')'>,9:0]
[@57,338:338=';',<';'>,9:1]
[@58,339:339='\n',<White_space>,channel=1,9:2]
[@59,340:387='//---------------------------------------------\n',<One_line_comment>,channel=1,10:0]
[@60,388:437='// the following localparam need to configure to \n',<One_line_comment>,channel=1,11:0]
[@61,438:464='// fit defferent scenarios\n',<One_line_comment>,channel=1,12:0]
[@62,465:512='//---------------------------------------------\n',<One_line_comment>,channel=1,13:0]
[@63,513:528='/*\noutput aa;\n*/',<Block_comment>,channel=1,14:0]
[@64,529:529='\n',<White_space>,channel=1,16:2]
[@65,530:538='endmodule',<'endmodule'>,17:0]
[@66,539:539='\n',<White_space>,channel=1,17:9]
[@67,540:539='<EOF>',<EOF>,18:0]
➜ verilog pwd
/Users/qilei/Downloads/grammars-v4-master/verilog/verilog
➜ verilog
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